A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip

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A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip

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Great Lakes Symposium on VLSI archive
Proceedings of the 18th ACM Great Lakes symposium on VLSI table of contents

Orlando, Florida, USA

SESSION: Session 1B: Addressing Emerging Technology Issues in VLSI Circuits table of contents

Pages 47-52

Year of Publication: 2008

ISBN:978-1-59593-999-9

Authors

Dhruva Ghai	University of North Texas, Denton, TX, USA
Saraju Mohanty	University of North Texas, Denton, TX, USA
Elias Kougianos	University of North Texas, Denton, TX, USA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery

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ACM New York, NY, USA

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Downloads (6 Weeks): 11, Downloads (12 Months): 102, Citation Count: 0

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ABSTRACT

This paper presents a process variation tolerant, SoC ready, 1 GS/s, 6 bit flash analog-to-digital converter (ADC) suitable for integration into nanoscale digital CMOS technologies. The physical design is carried out with a generic 90 nm Salicide 1.2 V/2.5 V 1 Poly 9 Metal process design kit using Design for Manufacturability (DFM) methodologies. Post-layout simulation results at nominal supply and threshold voltages are presented. The parasitic-extracted physical design of the ADC has been simulated for a supply voltage variation of 10%, and threshold voltage mismatch of 5%. The results show maximum variations of 10.5% and 5.7% in the INL and DNL respectively, with nominal INL = 0.344 LSB and nominal DNL = 0.459 LSB, at a supply voltage of 1.2 V. The ADC consumes a peak power of 5.794 mW and an average power of 3.875 mW. The comparators used in the ADC have been designed using the threshold inverting technique.

REFERENCES

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