| Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators |
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Great Lakes Symposium on VLSI
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Proceedings of the 18th ACM Great Lakes symposium on VLSI
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Orlando, Florida, USA
SESSION: Session 1B: Addressing Emerging Technology Issues in VLSI Circuits
table of contents
Pages 41-46
Year of Publication: 2008
ISBN:978-1-59593-999-9
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Authors
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Basab Datta
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University of Massachusetts-Amherst, Amherst, MA, USA
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Wayne Burleson
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University of Massachusetts-Amherst, Amherst, MA, USA
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Downloads (6 Weeks): 6, Downloads (12 Months): 51, Citation Count: 0
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ABSTRACT
High die temperatures adversely impact CMOS circuit operation degrading performance and reliability of both devices and interconnect. Current thermal scaling trends in multilevel low-k interconnect structures suggest an increasing heat density for the metal layers as a result of which the temperature dependence of logic is matched or often exceeded by that of interconnect. This motivates the need to perform 3-D thermal sensing in deep nanometer designs. We propose a novel sensor design that alleviates the complexities associated with time-to-digital conversion in wire-based thermal sensing. The sensing circuit makes use of wire-segments between individual stages of a ring-oscillator to perform thermal sensing using the oscillator frequency value as the mapping to corresponding wire temperature. Alternatively, the sensor can be tuned to strengthen the thermal sensitivity of the devices over that of interconnects to perform substrate-based sensing. We propose a collaborative scheme to sample the thermal status of the different metal levels and the substrate. The proposed sensor provides a resolution of 1°C while consuming an active power of 65-112µW and its sensitivity to process and supply noise can be minimized through design optimizations.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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