On-die CMOS voltage droop detection and dynamiccompensation

ABSTRACT

This paper describes an on-die di/dt voltage droop compensation scheme for use in high current, low voltage, VLSI circuits using current injection. The circuit was designed and simulated with SPICE. The circuit is able to source up to 150mA of current into a drooping node, has a bandwidth of 20MHz, and is able to lessen voltage droop magnitude. Since there is delay between the droop event and the current provided by this circuit, a predictive current injection scheme is proposed and some simulation and analysis of this method is performed.

REFERENCES

• 1: E. Alon, V. Stojanovic, and M. Horowitz. Circuits and techniques for high-resolution measurement of on--chip power supply noise. In VLSI Circuits Digest of Technical Papers, pages 102--105, June 2004.
• 2: H. Aoki, M. Ikeda, and K. Asada. On-chip voltage noise monitor for measuring voltage bounce in power supply lines using a digital tester. In International Conference on Microelectronic Test Structures, pages 112--117, 2000.
• 3: Geng Bai , Sudhakar Bobba , Ibrahim N. Hajj, Static timing analysis including power supply noise effect on propagation delay in VLSI circuits, Proceedings of the 38th conference on Design automation, p.295-300, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.378489]
• 4: C. Chansungsan. Auto-referenced on-die power supply noise measurement circuit. In IEEE Custom Integrated Circuits Conference, pages 39--42, September 2005.
• 5: Intel Corporation. Intel Processor QX6000 Sequence and Q6000 Sequence Datasheet. Microprocessor Databook.
• 6: Suhwan Kim , Stephen V. Kosonocky , Daniel R. Knebel, Understanding and minimizing ground bounce during mode transition of power gating structures, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871515]
• 7: A. Muhtaroglu, G. Taylor, and T. Rahal--Arabi. On-die droop detector for analog sensing of power supply noise. IEEE J. Solid-State Circuits, 39(4):651--660, April 2004.
• 8: T. Nakura, M. Ikeda, and K. Asada. Power supply noise reduction using stubs. IEICE technical report, 103(480):217--222, 2003.
• 9: T. Rahal--Arabi, G. Taylor, M. Ma, and C. Webb. Design and validation of the Pentium III and Pentium 4 processors power delivery. In Symposium On VLSI Circuits Digest of Technical Papers, pages 220--223, June 2002.
• 10: R. Senthinathan and J. Prince. Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise. IEEE J. Solid-State Circuits, 28(12):1383--1388, December 1993.
• 11: L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy. Power distribution system design methodology and capacitor selection for modern CMOS technology. IEEE Trans. Adv. Packag., 22(3):284--291, August 1999.
• 12: K. L. Wong, T. Rahal-Arabi, M. Ma, and G. Taylor. Enhancing microprocessor immunity to power supply noise with clock-data compression. IEEE J. Solid-State Circuits, 41(4):749--758, April 2006.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

General Terms:
Design, Performance, Reliability, Verification

Keywords:
di/dt voltage droop, on-die voltage droop compensation, power supply droop, predictive current injection