Filtering drowsy instruction cache to achieve better efficiency

ABSTRACT

Leakage power in cache memories represents a sizable fraction of total power consumption, and many techniques have been proposed to reduce it. As a matter of fact, during a fixed period of time, only a small subset of cache lines is used. Previous techniques put unused lines, for example, to drowsy in order to save power.

Our idea is to adaptively select the most used cache lines. In the case of instruction cache, we found that this can automatically achieved by coupling a tiny cache acting as a filter cache (ILO cache) with a drowsy-cache.

Our experiments, with complete MiBench suite for ARM based processor, show a 25% improvement in leakage saving versus drowsy.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

General Terms:
Design, Experimentation, Performance

Keywords:
drowsy cache, filter cache, leakage, low-power