|
ABSTRACT
We propose a general framework for improving the query processing performance on multi-level memory hierarchies. Our motivation is that (1) the memory hierarchy is an important performance factor for query processing, (2) both the memory hierarchy and database systems are becoming increasingly complex and diverse, and (3) increasing the amount of tuning does not always improve the performance. Therefore, we categorize multiple levels of memory performance tuning and quantify their performance impacts. As a case study, we use this framework to improve the in-memory performance of storage models, B+-trees, nested-loop joins and hash joins. Our empirical evaluation verifies the usefulness of the proposed framework.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
| |
2
|
|
| |
3
|
|
| |
4
|
AMD Corp. Software Optimization Guide for AMD64 Processors, 2005.
|
| |
5
|
|
| |
6
|
|
 |
7
|
|
| |
8
|
R. Berrendorf, H. Ziegler, and B. Mohr. PCL: Performance Counter Library. http://www.fz-juelich.de/zam/PCL/, 2002.
|
 |
9
|
Philip Bohannon , Peter Mcllroy , Rajeev Rastogi, Main-memory index structures with fixed-size partial keys, Proceedings of the 2001 ACM SIGMOD international conference on Management of data, p.163-174, May 21-24, 2001, Santa Barbara, California, United States
|
| |
10
|
|
| |
11
|
|
| |
12
|
G. S. Brodal, R. Fagerberg, and K. Vinther. Engineering a cache-oblivious sorting algorith. In ALENEX/ANALC, pages 4--17, 2004.
|
| |
13
|
|
| |
14
|
|
 |
15
|
|
 |
16
|
|
 |
17
|
Trishul M. Chilimbi , Mark D. Hill , James R. Larus, Cache-conscious structure layout, Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation, p.1-12, May 01-04, 1999, Atlanta, Georgia, United States
|
| |
18
|
|
| |
19
|
Amol Ghoting , Gregory Buehrer , Srinivasan Parthasarathy , Daehyun Kim , Anthony Nguyen , Yen-Kuang Chen , Pradeep Dubey, Cache-conscious frequent pattern mining on a modern processor, Proceedings of the 31st international conference on Very large data bases, August 30-September 02, 2005, Trondheim, Norway
|
| |
20
|
|
| |
21
|
N. Hardavellas, I. Pandis, R. Johnson, N. Mancheril, S. Harizopoulos, A. Ailamaki, and B. Falsafi. Database servers on chip multiprocessors: Limitations and opportunities. In CIDR '07: Proceedings of the Third International Conference on Innovative Data Systems Research, Asilomar, CA, USA, 2007.
|
 |
22
|
|
 |
23
|
|
 |
24
|
|
| |
25
|
B. He and Q. Luo. Cache-oblivious query processing. In CIDR '07: Proceedings of the Third International Conference on Innovative Data Systems Research, Asilomar, CA, USA, 2007.
|
| |
26
|
Intel Corp. Intel(R) Itanium(R) 2 Processor Reference Manual for Software Development and Optimization, 2004.
|
 |
27
|
|
| |
28
|
|
| |
29
|
|
 |
30
|
|
| |
31
|
|
| |
32
|
Sun Corp. UltraSPARC (R) III Cu Users Manual, 1997.
|
| |
33
|
|
|