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Parallel buffers for chip multiprocessors
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Source Data Management On New Hardware archive
Proceedings of the 3rd international workshop on Data management on new hardware table of contents
Beijing, China
SESSION: Multi-core, multi-threading, and deep memory hierarchies table of contents
Article No. 2  
Year of Publication: 2007
ISBN:978-1-59593-772-8
Authors
John Cieslewicz  Columbia University
Kenneth A. Ross  Columbia University
Ioannis Giannakakis  Columbia University
Sponsor
SIGMOD: ACM Special Interest Group on Management of Data
Publisher
ACM  New York, NY, USA
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ABSTRACT

Chip multiprocessors (CMPs) present new opportunities for improving database performance on large queries. Because CMPs often share execution, cache, or bandwidth resources among many hardware threads, implementing parallel database operators that efficiently share these resources is key to maximizing performance. A crucial aspect of this parallelism is managing concurrent, shared input and output to the parallel operators. In this paper we propose and evaluate a parallel buffer that enables intra-operator parallelism on CMPs by avoiding contention between hardware threads that need to concurrently read or write to the same buffer. The parallel buffer handles parallel input and output coordination as well as load balancing so individual operators do not need to reimplement that functionality.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
John Cieslewicz: colleagues
Kenneth A. Ross: colleagues
Ioannis Giannakakis: colleagues