| Pipelined hash-join on multithreaded architectures |
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Data Management On New Hardware
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Proceedings of the 3rd international workshop on Data management on new hardware
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Beijing, China
SESSION: Multi-core, multi-threading, and deep memory hierarchies
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Article No. 1
Year of Publication: 2007
ISBN:978-1-59593-772-8
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Downloads (6 Weeks): 14, Downloads (12 Months): 69, Citation Count: 0
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ABSTRACT
Multi-core and multithreaded processors present both opportunities and challenges in the design of database query processing algorithms. Previous work has shown the potential for performance gains, but also that, in adverse circumstances, multithreading can actually reduce performance. This paper examines the performance of a pipeline of hash-join operations when executing on multithreaded and multicore processors. We examine the optimal number of threads to execute and the partitioning of the workload across those threads. We then describe a buffer-management scheme that minimizes cache conflicts among the threads. Additionally we compare the performance of full materialization of the output at each stage in the pipeline versus passing pointers between stages.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Intel multi-core processor architecture development backgrounder. Intel White Paper, 2005.
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2
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Multi-core processors -- the next evolution in computing. AMD White Paper, 2005.
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3
|
Throughput computing: Changing the economics and ecology of the data center with innovative SPARC® technology. Sun Microsystems White Paper, November 2005.
|
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4
|
|
| |
5
|
|
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6
|
D. Carmean. Data management challenges on new computer architectures. In First Int'l Workshop on Data Management on New Hardware (DaMoN), June 2005. Oral Presentation.
|
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7
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8
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Susan J. Eggers , Joel S. Emer , Henry M. Levy , Jack L. Lo , Rebecca L. Stamm , Dean M. Tullsen, Simultaneous Multithreading: A Platform for Next-Generation Processors, IEEE Micro, v.17 n.5, p.12-19, September 1997
[doi> 10.1109/40.621209]
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9
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10
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P. C. Garcia. Optimizing database algorithms for modern computer architectures. Master's thesis, August 2005. http://www.cse.lehigh.edu/~pcg2/thesis.pdf.
|
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11
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Naga Govindaraju , Jim Gray , Ritesh Kumar , Dinesh Manocha, GPUTeraSort: high performance graphics co-processor sorting for large database management, Proceedings of the 2006 ACM SIGMOD international conference on Management of data, June 27-29, 2006, Chicago, IL, USA
[doi> 10.1145/1142473.1142511]
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13
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14
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R. Kalla, B. Sinharoy, and J. M. Tendler. IBM Power5 chip: A dual-core multithreaded processor. 2004.
|
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15
|
M. Kitsuregawa, H. Tanaka, and T. Moto-Oka. Application of hash to data base machine and its architecture. In New Generation Computing, volume 1, pages 63--74, 1983.
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16
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D. T. Marr, F. Binns, D. L. Hill, G. Hinton, D. A. Koufaty, J. A. Miller, and M. Upton. Hyper-threading technology architecture and microarchitecture. Intel Technology Journal, (Q1):4--15, 2002.
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17
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F. Mueller. Pthreads library interface, 1993.
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18
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S. Oks. Be aware: To hyper or not to hyper. Slava Oks Weblog http://blogs.msdn.com/slavao/archive/-2005/11/12/492119.aspx, Nov 2005.
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19
|
P. S. Otellini. Multi-core enables performance without power penalties. In Intel Developer Forum Keynote, http://www.embedded-controleurope.com/pdf/-ecedec05p26.pdf, 2005.
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20
|
|
| |
21
|
D. Towner and D. May. The 'uniform heterogeneous multi-threaded' processor architecture. In A. Chalmers, M. Mirmehdi, and H. Muller, editors, Communicating Process Architectures - 2001, pages 103--116. IOS Press, September 2001.
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22
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Dean M. Tullsen , Susan J. Eggers , Joel S. Emer , Henry M. Levy , Jack L. Lo , Rebecca L. Stamm, Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor, Proceedings of the 23rd annual international symposium on Computer architecture, p.191-202, May 22-24, 1996, Philadelphia, Pennsylvania, United States
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