| GRAPE-DR: 2-Pflops massively-parallel computer with 512-core, 512-Gflops processor chips for scientific computing |
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Conference on High Performance Networking and Computing
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Proceedings of the 2007 ACM/IEEE conference on Supercomputing - Volume 00
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Reno, Nevada
SESSION: System architecture
table of contents
Article No. 18
Year of Publication: 2007
ISBN:978-1-59593-764-3
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Downloads (6 Weeks): 9, Downloads (12 Months): 70, Citation Count: 1
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ABSTRACT
We describe the GRAPE-DR (Greatly Reduced Array of Processor Elements with Data Reduction) system, which will consist of 4096 processor chips each with 512 cores operating at the clock frequency of 500 MHz. The peak speed of a processor chip is 512Gflops (single precision) or 256 Gflops (double precision). The GRAPE-DR chip works as an attached processor to standard PCs. Currently, a PCI-X board with single GRAPE-DR chip is in operation. We are developing a 4-chip board with PCI-Express interface, which will have the peak performance of 1 Tflops. The final system will be a cluster of 512 PCs each with two GRAPE-DR boards. We plan to complete the final system by early 2009. The application area of GRAPE-DR covers particle-based simulations such as astrophysical many-body simulations and molecular-dynamics simulations, quantum chemistry calculations, various applications which requires dense matrix operations, and many other compute-intensive applications.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY
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Hiroshige Hayashizaki , Yutaka Sugawara , Mary Inaba , Kei Hiraki, MCAMP: communication optimization on massively parallel machines with hierarchical scratch-pad memory, Proceedings of the 17th international conference on Parallel architectures and compilation techniques, October 25-29, 2008, Toronto, Ontario, Canada
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