ACM Home Page
Please provide us with feedback. Feedback
Symbolic Boolean manipulation with ordered binary-decision diagrams
Full text PdfPdf (2.12 MB)
Source ACM Computing Surveys (CSUR) archive
Volume 24 ,  Issue 3  (September 1992) table of contents
Pages: 293 - 318  
Year of Publication: 1992
ISSN:0360-0300
Author
Randal E. Bryant  School of Computer Science, Carnegie-Mellon University, Pittsburgh, Pennsylvania
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 38,   Downloads (12 Months): 298,   Citation Count: 229
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/136035.136043
What is a DOI?

ABSTRACT

Ordered Binary-Decision Diagrams (OBDDs) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satisfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD data structures. Using OBDDs, a wide variety of problems can be solved through symbolic analysis. First, the possible variations in system parameters and operating conditions are encoded with Boolean variables. Then the system is evaluated for all variations by a sequence of OBDD operations. Researchers have thus solved a number of problems in digital-system design, finite-state system analysis, artificial intelligence, and mathematical logic. This paper describes the OBDD data structure and surveys a number of applications that have been solved by OBDD-based symbolic analysis.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
2
S. B. 1978. Binary decision diagrams. IEEE Trans. Comput. C-27, 6 (Aug.), 509 516.
 
3
4
 
5
C. L. 1989. Ordered binary decision diagrams and circuit structure. In The International Conference on Computer Design (Cambridge, Mass., Oct.), IEEE, New York, pp. 392 395.
 
6
M. W., AND CHANDRA, A.K. 1980. Equivalence of free Boolean graphs can be decided probabilistically in polynomial time. Inf. Process. Lett. 10, 2 (Mar.), 80-82.
 
7
S., AND FISHER, A. L. 1989. Verifying pipelined hardware using symbolic logic simulation. In The International Conference on Computer Deszgn (Boston, Oct.). IEEE, New York, pp. 217 221.
8
 
9
 
10
F., POWNALL, P., AND HUM, P. 1984. Apphcations of testability analysis: From ATPG to critical path tracing. In The International Test Conference (Philadelphia, Oct.). IEEE, New York, pp. 705-712.
 
11
F.M. 1990. Boolean Reasoning. Kluwer Academic Publishers, Boston
 
12
 
13
14
 
15
J. R., CLARKE, E. M., AND McMmLAN, K. 1990a. Symbolic model checking: 102~ states and beyond In The 5th Annual IEEE Symposium on Logic in Computer Science (Philadelphia, June) IEEE, New York, pp. 428 439
16
 
17
 
18
E., AND MAmN, M.A. 1977. An approach to unified methodology of combinational switching circuits. IEEE Trans. Comput. C-26, 8 (Aug.), 745 756.
19
20
 
21
22
 
23
 
24
, T. 1991. A method for symbolic verification of synchronous circuits. In Computer Hardware Description Languages and their Applications (Marseilles, Apr.). Proceedings of IFIP WG 10.2, Tenth International Symposium Amsterdam, North-Holland, D. Borrione and R. Waxman, Eds., pp. 229-239.
 
25
 
26
, M., FUJISAWA, H., AND KAWATO, N. 1988. Evaluations and improvements of a Boolean comparison program based on binary decision diagrams. In The International Conference on Computer-Aided Destgn (Santa Clara. Calif., Nov.). 1EEE, New York, pp. 2 5.
 
27
M., KAK~TDA, T., AND MATSUNAGA, Y. 1991. Redesign and automatic error correction of combinational circuits. In Logic and Architecture Synthesis: Proceedings of the IFIP TCIO / WGIO. 5 Workshop on Logic and Architecture Synthesis (Paris, May 1990), P. Michel and G. Saucier, Eds. Elsevier, Amsterdam, pp. 35~ ~go.
 
28
M. R., AND JOHNSON, D.S. 1979. Computers and Intractability. W. H. Freeman and Company, New York.
 
29
J., AND MEINEL, C. 1992. Efficient analysis and manipulation of OBDDs can be extended to read-once-only branching programs. Tech. Rep. 92-10, Universit~it Trier, Fachbereich IV--Mathematik/ Informatik, Trier, Germany.
30
 
31
EONG, S.-W., PLESSIER, B., HACHTEL, G. D., AND SOMENZL F. 1991. Variable ordering and selection for FSM traversal. In The International Conference on Computer-Aided Design (Santa Clara, Calif., Nov.). IEEE, New York, pp. 476-479.
 
32
 
33
IMURA, S., AND CLARK, E. M. 1990. A parallel algorithm for constructing binary decision diagrams. In The International Conference on Computer Design (Boston, Oct.). IEEE, New York, pp. 220-223.
 
34
E, C.Y. 1959. Representation of switching circuits by binary-decision programs. Bell System Tech. J. 38, 4(July), 985-999.
 
35
LIN, B., TOUATI, H. J., AND NEWTON, A.R. 1990. Don't care minimization of multi-level sequential logic networks. In The Internatwnal Conference on Computer-Aided Destgn (Santa Clara, Calif., Nov.). IEEE, New York, pp. 4{4 417.
 
36
 
37
MADRE, J.-C., AND COUDERT, O. 1991. A logically complete reasoning maintenance system based on a logical constraint solver. In The 12th International Joint Conference on Artificial Intelligence (Sydney, Aug.), Morgan Kaufman, San Mateo, CA, pp. 294-299.
 
38
MADRE, J.-C, COUDERT, O., AND BILLON, J.P. 1989. Automating the diagnosis and rectification of design errors with PRIAM. In The Internatwnal Conference on Computer-A~ded Design (Santa Clara, Calif., Nov.). IEEE, New York, pp. 30-33.
 
39
MALIK, S., WANG, A., BRAYTON, R. K., AND SANGIOVANNI-VINCENTELLI, A. 1988. Logic verification using binary decision diagrams in a logic synthes~s environment. In The International Conference on Computer-Aided Design (Santa Clara, Calif., Nov.). IEEE, New York, pp. 6-9.
 
40
MCMmLAN, K. L. 1992. Symbolic model checking: An approach to the state explosion problem. PhD thesis, School of Computer Science, Carnegie-Mellon Univ.
 
41
 
42
43
44
 
45
REEVES, D. S., AND IRWIN, M.J. 1987. Fast methods for switch-level verification of MOS circuits. IEEE Trans. CAD / IC CAD-G, 5 (Sept.), 766-779.
46
 
47
SELLERS, F. F., HSIAO, M. Y., AND BEARNSON, C. L. 1968. Analyzing errors with the Boolean difference. IEEE Trans. Comput. C-17, 7(July), 676 683.
 
48
SRINIVASAN, A., KAM, T., MALIK, S., AND BRAYTON, R.K. 1990. Algorithms for discrete function manipulation. In The Internattonal Conference on Computer-Aided Design (Santa Clara, Calif., Nov.). IEEE, New York, pp. 92-95.
49

CITED BY  229