ACM Home Page
Please provide us with feedback. Feedback
Program optimization space pruning for a multithreaded gpu
Full text PdfPdf (523 KB)
Source
Code Generation and Optimization archive
Proceedings of the sixth annual IEEE/ACM international symposium on Code generation and optimization table of contents
Boston, MA, USA
SESSION: Compiling for multicore and multithreading table of contents
Pages 195-204  
Year of Publication: 2008
ISBN:978-1-59593-978-4
Authors
Shane Ryoo  University of Illinois at Urbana-Champaign, Urbana, IL, USA
Christopher I. Rodrigues  University of Illinois at Urbana-Champaign, Urbana, IL, USA
Sam S. Stone  University of Illinois at Urbana-Champaign, Urbana, IL, USA
Sara S. Baghsorkhi  University of Illinois at Urbana-Champaign, Urbana, IL, USA
Sain-Zee Ueng  University of Illinois at Urbana-Champaign, Urbana, IL, USA
John A. Stratton  University of Illinois at Urbana-Champaign, Urbana, IL, USA
Wen-mei W. Hwu  University of Illinois at Urbana-Champaign, Urbana, IL, USA
Sponsors
ACM: Association for Computing Machinery
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
SIGPLAN: ACM Special Interest Group on Programming Languages
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 43,   Downloads (12 Months): 317,   Citation Count: 12
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1356058.1356084
What is a DOI?

ABSTRACT

Program optimization for highly-parallel systems has historically been considered an art, with experts doing much of the performance tuning by hand. With the introduction of inexpensive, single-chip, massively parallel platforms, more developers will be creating highly-parallel applications for these platforms, who lack the substantial experience and knowledge needed to maximize their performance. This creates a need for more structured optimization methods with means to estimate their performance effects. Furthermore these methods need to be understandable by most programmers. This paper shows the complexity involved in optimizing applications for one such system and one relatively simple methodology for reducing the workload involved in the optimization process.

This work is based on one such highly-parallel system, the GeForce 8800 GTX using CUDA. Its flexible allocation of resources to threads allows it to extract performance from a range of applications with varying resource requirements, but places new demands on developers who seek to maximize an application's performance. We show how optimizations interact with the architecture in complex ways, initially prompting an inspection of the entire configuration space to find the optimal configuration. Even for a seemingly simple application such as matrix multiplication, the optimal configuration can be unexpected. We then present metrics derived from static code that capture the first-order factors of performance. We demonstrate how these metrics can be used to prune many optimization configurations, down to those that lie on a Pareto-optimal curve. This reduces the optimization space by as much as 98% and still finds the optimal configuration for each of the studied applications.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
NVIDIA CUDA. http://www.nvidia.com/cuda.
 
2
SPIRAL project. http://spiral.net.
 
3
4
5
 
6
W. Blume et al. Polaris: The next generation in parallelizing compilers. Technical Report 1375, University of Illinois at Urbana--Champaign, 1994.
 
7
I. Buck. Brook Specification v0.2, October 2003.
8
9
10
 
11
 
12
H. Han, G. Rivera, and C.--W. Tseng. Software support for improving locality in scientific codes. In 8th Workshop on Compilers for Parallel Computers, January 2000.
 
13
 
14
 
15
D. Jimenez--Gonzalez, X. Martorell, and A. Ramirez. Performance analysis of Cell Broadband Engine for high memory bandwidth applications. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, pages 210--219, April 2007.
 
16
 
17
 
18
19
 
20
J. Nickolls and I. Buck. NVIDIA CUDA software and GPU parallel computing architecture. Microprocessor Forum, May 2007.
 
21
NVIDIA Corporation. CUDA Programming Guide, February 2007.
22
 
23
J. E. Stone et al. Accelerating molecular modeling applications with graphics processors. Journal of Computational Chemistry, 28(16):2618--2640, December 2007.
 
24
S. Stone et al. How GPUs can improve the quality of magnetic resonance imaging. The First Workshop on General Purpose Processing on Graphics Processing Units, October 2007.
25
 
26
 
27
 
28
29

CITED BY  12

Collaborative Colleagues:
Shane Ryoo: colleagues
Christopher I. Rodrigues: colleagues
Sam S. Stone: colleagues
Sara S. Baghsorkhi: colleagues
Sain-Zee Ueng: colleagues
John A. Stratton: colleagues
Wen-mei W. Hwu: colleagues