Implications of device timing variability on full chip timing

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Implications of device timing variability on full chip timing

Full text

Pdf (153 KB)

Source

International Symposium on Physical Design archive
Proceedings of the 2008 international symposium on Physical design table of contents

Portland, Oregon, USA

SESSION: Statistical and physical design for manufacturability -- act II table of contents

Pages 68-68

Year of Publication: 2008

ISBN:978-1-60558-048-7

Authors

Ed Grochowski	Intel Corporation, Santa Clara, CA, USA
Murali Annavaram	University of Southern California, Los Angeles, CA, USA
Paul Reed	Intel Corporation, Austin, TX, USA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 29, Citation Count: 0

Additional Information:

abstract references index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/1353629.1353644 What is a DOI?

ABSTRACT

As process technologies continue to scale, the magnitude of within-die device parameter variations is expected to increase and may lead to significant timing variability. This talk presents a quantitative evaluation of how low level device timing variations impact the timing at the functional block level. We evaluate two types of timing variations: random and systematic variations. The study introduces random and systematic timing variations to several functional blocks in Intel® Core™ Duo microprocessor design database and measures the resulting timing margins. The primary conclusion of this research is that as a result of combining two probability distributions (the distribution of the random variation and the distribution of path timing margins) functional block timing margins degrade non-linearly with increasing variability

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

Murali Annavaram , Ed Grochowski , Paul Reed, Implications of Device Timing Variability on Full Chip Timing, Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, p.37-45, February 10-14, 2007 [doi>10.1109/HPCA.2007.346183]

INDEX TERMS

Primary Classification:
B. Hardware
B.8 Performance and Reliability
B.8.0 General