Global interconnections in FPGAs: modeling and performance analysis

ABSTRACT

This paper presents a new model forglobal routings in FPGAs. The irregular interconnections in FPGAs can be generalized as multiple buffered interconnect stages, of which the electrical waveform can be adequately approximated. Based on the model, expressions of delay and fundamental throughput of the interconnections have been derived and validated. They are shown in line with the SPICE and FPGA experimental results. Moreover, the model shows that interconnection throughput can be significantly increased using wave-pipelined signaling instead of the conventional delay-based synchronous approach, as has been demonstrated in our FPGA experiments. We conclude this paper by having a discussion about a strategy to further enhance the interconnect throughput.

REFERENCES

• 1: H. Bakoglu. Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley Publishing Company, 1990.
• 2: Vaughn Betz , Jonathan Rose , Alexander Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, Norwell, MA, 1999
• 3: Crescenzo D'Alessandro , Andrey Mokhov , Alex Bystrov , Alex Yakovlev, Delay/Phase Regeneration Circuits, Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems, p.105-116, March 12-14, 2007 [doi>10.1109/ASYNC.2007.14]
• 4: V. Deodhar and J. Davis. Optimization of Throughput Performance for Low-Power VLSI Interconnects. IEEE Trans. on VLSI Systems, 13(3):308--318, 2005.
• 5: A. Donlin and B. New. Method and Apparatus for Communication within a Prorammable Logic Device Using Serial Transceivers. US Patent No. 7062586 B2, 2006.
• 6: R. Ho, K. Mai, and M. Horowitz. The Future of Wires. Proceedings of the IEEE, 89(4):490--504, 2001.
• 7: A. Joshi, G. Lopez, and J. Davis. Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. IEEE Trans. on VLSI Systems, 15(9):990--1002, 2007.
• 8: E. Lee, G. Lemieux, and S. Mirabbasi. Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays. In Proceedings of the International Conference on Field-Programmable Technology, 2006.
• 9: G. Lemieux, E. Lee, M. Tom, and A. Yu. Directional and Single-Driver Wires in FPGA Interconnect. In Proceedings of the International Conference on Field-Programmable Technology, 2004.
• 10: Liang-Yu Lin , Cheng-Yeh Wang , Pao-Jui Huang , Chih-Chieh Chou , Jing-Yang Jou, Communication-driven task binding for multiprocessor with latency insensitive network-on-chip, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China [doi>10.1145/1120725.1120739]
• 11: Dinesh Pamunuwa , Li-Rong Zheng , Hannu Tenhunen, Maximizing throughput over parallel wire structures in the deep submicrometer regime, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.2, p.224-243, April 2003 [doi>10.1109/TVLSI.2003.810800]
• 12: Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
• 13: T. Sakurai. Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI. IEEE Trans. on Electron Devices, 40(1):118--124, 1993.
• 14: Harshit Shah , Pun Shiu , Brian Bell , Mamie Aldredge , Namarata Sopory , Jeff Davis, Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.280-284, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774614]
• 15: G. Wang, S. Sivaswamy, C. Ababei, K. Bazargan, R. Kastner, and E. Bozorgzadeh. Statistical Analysis and Design of HARP FPGAs. IEEE Trans. on VLSI Systems, 14(7), 2006.
• 16: Xilinx. FPGA Editor Guide -- 3.1i. 2000.
• 17: Xilinx. Virtex-4 Data Sheets. 2005.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Logic arrays

General Terms:
Performance, Theory

Keywords:
FPGA, interconnection, throughput, wave-pipelined