A soft error analysis tool for high-speed digital designs

ABSTRACT

Evaluation of soft error hardness becomes more important for modern electrical and electronic devices as the semi-conductor technology advances. Recent studies have mainly focused on soft error rate analysis of combinational logic circuits which has been used with simulation and/or path-based statistical estimation. Only a few studies suggested the techniques for evaluating sequential circuits. To assess soft error susceptibility for general cell-based designs, it is essential to analyze variation of total SER between clock-to-clock transitions as well as initial soft error rates. This paper presents a two-pass soft error analysis technique, which provides both initial and dynamic error rate of digital circuits. Especially, the logical probabilities for noise generation and propagation are considered in detail without much computational complexity. Experimental results are reported from a pre-characterized 130nm technology cell library.

REFERENCES

• 1: M. Zhang, N. R. Shanbhag, "Soft-Error-Rate-Analysis (SERA) Methodology," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 10, pp.2140--2155, 2006.
• 2: Y. S. Dhillon, A. U. Diril, A. Chatterjee, and A. D. Singh, "Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance," IEEE Trans. on VLSI Systems, Vol. 14, No. 5, pp.514--524, 2006.
• 3: Kartik Mohanram , Nur A. Touba, Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits, Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, p.433, November 03-05, 2003
• 4: Hossein Asadi , Mehdi B. Tahoori, Soft Error Modeling and Protection for Sequential Elements, Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, p.463-474, October 03-05, 2005 [doi>10.1109/DFTVS.2005.61]
• 5: Natasa Miskov-Zivanov , Diana Marculescu, MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits, Proceedings of the 8th International Symposium on Quality Electronic Design, p.893-898, March 26-28, 2007 [doi>10.1109/ISQED.2007.100]
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.0 General
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids
  B.m MISCELLANEOUS
      Subjects: Design management

General Terms:
Design, Performance, Verification