|
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
 |
2
|
|
 |
3
|
|
 |
4
|
|
| |
5
|
|
 |
6
|
|
| |
7
|
Dantzig, G.B. and Eaves, B,C. Fourier-Motzkin elimination and its dual. J. Combin. Theo. A, 14 (1973), 288-297.
|
 |
8
|
Gina Goff , Ken Kennedy , Chau-Wen Tseng, Practical dependence testing, Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, p.15-29, June 24-28, 1991, Toronto, Ontario, Canada
|
| |
9
|
Haghighat, M. and Poiychronopoutos, C. Symbolic dependence analysis for high Performance parallelizing compilers. In Proceed.. ings of the Third Workshop on Languages and Compilers for Parallel Com.. puting, Aug. 1990.
|
| |
10
|
|
 |
11
|
|
| |
12
|
Klappholz, D. and Kong, X, Extending the Bane{jee-Wolfe test to handle execution conditions. Tech. Rep. 9101, Dept. of EE/CS, Stevens Institute of' Technology, 199i.
|
| |
13
|
Kuck, D., Muraoka, Y. and Chen, S. On the number of operations simultaneousiy executable in Fortrandike programs and their resulting speedup. IEEE Trans. Comput., 1972.
|
| |
14
|
|
 |
15
|
|
 |
16
|
|
| |
17
|
|
 |
18
|
Dror E. Maydan , John L. Hennessy , Monica S. Lam, Efficient and exact data dependence analysis, Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, p.1-14, June 24-28, 1991, Toronto, Ontario, Canada
|
| |
19
|
|
 |
20
|
|
 |
21
|
|
| |
22
|
Triolet, R. Interprocedural analysis for program restructuring with Parafrase. CSRD R.ep, 538, Dept. of Computer Science, University of Illinois at Urbana-Champaign, Dec. 1985.
|
 |
23
|
|
| |
24
|
Wotft:, Md. Optimizing supercompilers f'or supercomputers. PhD thesis, Dept, of Computer Science, University of Illinois at Urbanao Champaign, Oct, 1982,
|
| |
25
|
WolIie, M. Optimizing Supercompiters for Supercomputers. Pitman Publishing, London, 1989.
|
| |
26
|
Wolfe, M. The tiny loop restructur ing resea:rch tool. In Proceedings o{' 1991 lnternationat Conference on Para allel Processing, 1991.
|
| |
27
|
Wolfe, M. and Tseng, C, The power test for data dependence. Tech. Rep CS/E 90-015, Oregon Graduate Institme, Aug. 1990.
|
CITED BY 155
|
|
|
|
|
|
|
|
|
|
|
Srivaths Ravi , Ganesh Lakshminarayana , Niraj K. Jha, Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.577-584, November 08-12, 1998, San Jose, California, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Nawaaz Ahmed , Nikolay Mateev , Keshav Pingali, Tiling imperfectly-nested loop nests, Proceedings of the 2000 ACM/IEEE conference on Supercomputing (CDROM), p.31-es, November 04-10, 2000, Dallas, Texas, United States
|
|
|
John Hughes , Lars Pareto , Amr Sabry, Proving the correctness of reactive systems using sized types, Proceedings of the 23rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages, p.410-423, January 21-24, 1996, St. Petersburg Beach, Florida, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Denis Barthou , Albert Cohen , Jean-François Collard, Maximal static expansion, Proceedings of the 25th ACM SIGPLAN-SIGACT symposium on Principles of programming languages, p.98-106, January 19-21, 1998, San Diego, California, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Tod Amon , Gaetano Borriello , Jiwen Liu, Making complex timing relationships readable: Presburger formula simplicication using don't cares, Proceedings of the 35th annual conference on Design automation, p.586-590, June 15-19, 1998, San Francisco, California, United States
|
|
|
|
|
|
|
|
|
William Blume , Rudolf Eigenmann , Jay Hoeflinger , David Padua , Paul Petersen , Lawrence Rauchwerger , Peng Tu, Automatic Detection of Parallelism: A Grand Challenge for High-Performance Computing, IEEE Parallel & Distributed Technology: Systems & Technology, v.2 n.3, p.37-47, September 1994
|
|
|
|
|
|
|
|
|
Allen Goldberg , T. C. Wang , David Zimmerman, Applications of feasible path analysis to program testing, Proceedings of the 1994 ACM SIGSOFT international symposium on Software testing and analysis, p.80-94, August 17-19, 1994, Seattle, Washington, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Yoji Yamada , John Gyllenhall , Grant Haab , Wen-mei Hwu, Data relocation and prefetching for programs with large data sets, Proceedings of the 27th annual international symposium on Microarchitecture, p.118-127, November 30-December 02, 1994, San Jose, California, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Ingrid M. Verbauwhede , Chris J. Scheers , Jan M. Rabaey, Memory estimation for high level synthesis, Proceedings of the 31st annual conference on Design automation, p.143-148, June 06-10, 1994, San Diego, California, United States
|
|
|
Tod Amon , Gaetano Borriello , Taokuan Hu , Jiwen Liu, Symbolic timing verification of timing diagrams using Presburger formulas, Proceedings of the 34th annual conference on Design automation, p.226-231, June 09-13, 1997, Anaheim, California, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Alexandru Turjan , Bart Kienhuis , Ed Deprettere, Translating affine nested-loop programs to process networks, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
S. W. Son , G. Chen , M. Kandemir , A. Choudhary, Exposing disk layout to compiler for reducing energy consumption of parallel disk based systems, Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming, June 15-17, 2005, Chicago, IL, USA
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Wei-Ngan Chin , Siau-Cheng Khoo , Shengchao Qin , Corneliu Popeea , Huu Hai Nguyen, Verifying safety policies with size properties and alias controls, Proceedings of the 27th international conference on Software engineering, May 15-21, 2005, St. Louis, MO, USA
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Cyrille Artho , Howard Barringer , Allen Goldberg , Klaus Havelund , Sarfraz Khurshid , Mike Lowry , Corina Pasareanu , Grigore Rosu , Koushik Sen , Willem Visser , Rich Washington, Combining test case generation and runtime verification, Theoretical Computer Science, v.336 n.2-3, p.209-234, 26 May 2005
|
|
|
Sumant Kowshik , Dinakar Dhurjati , Vikram Adve, Ensuring code safety without runtime checks for real-time control systems, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Albert Cohen , Sébastien Donadio , Maria-Jesus Garzaran , Christoph Herrmann , Oleg Kiselyov , David Padua, In search of a program generator to implement generic transformations for high-performance computing, Science of Computer Programming, v.62 n.1, p.25-46, September 2006
|
|
|
Arun Kejariwal , Alexandru Nicolau , Hideki Saito , Xinmin Tian , Milind Girkar , Utpal Banerjee , Constantine D. Polychronopoulos, A general approach for partitioning N-dimensional parallel nested loops with conditionals, Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures, July 30-August 02, 2006, Cambridge, Massachusetts, USA
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Muthu Manikandan Baskaran , Uday Bondhugula , Sriram Krishnamoorthy , J. Ramanujam , Atanas Rountev , P. Sadayappan, A compiler framework for optimization of affine loop nests for gpgpus, Proceedings of the 22nd annual international conference on Supercomputing, June 07-12, 2008, Island of Kos, Greece
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Robert Schreiber , Shail Aditya , Scott Mahlke , Vinod Kathail , B. Ramakrishna Rau , Darren Cronquist , Mukund Sivaraman, PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators, Journal of VLSI Signal Processing Systems, v.31 n.2, p.127-142, June 2002
|
|
|
Wei-Ngan Chin , Huu Hai Nguyen , Corneliu Popeea , Shengchao Qin, Analysing memory resource bounds for low-level programs, Proceedings of the 7th international symposium on Memory management, June 07-08, 2008, Tucson, AZ, USA
|
|
|
F. Balasa , P. G. Kjeldsberg , A. Vandecappelle , M. Palkovic , Q. Hu , H. Zhu , F. Catthoor, Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications, Journal of Signal Processing Systems, v.53 n.1-2, p.51-71, November 2008
|
|
|
Muthu Manikandan Baskaran , Nagavijayalakshmi Vydyanathan , Uday Kumar Reddy Bondhugula , J. Ramanujam , Atanas Rountev , P. Sadayappan, Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors, Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming, February 14-18, 2009, Raleigh, NC, USA
|
|
|
|
|
|
|
|
|
DaeGon Kim , Lakshminarayanan Renganarayanan , Dave Rostron , Sanjay Rajopadhye , Michelle Mills Strout, Multi-level tiling: M for the price of one, Proceedings of the 2007 ACM/IEEE conference on Supercomputing, November 10-16, 2007, Reno, Nevada
|
|
|
Muthu Manikandan Baskaran , Uday Bondhugula , Sriram Krishnamoorthy , J. Ramanujam , Atanas Rountev , P. Sadayappan, Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories, Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming, February 20-23, 2008, Salt Lake City, UT, USA
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Albert Hartono , Muthu Manikandan Baskaran , Cédric Bastoul , Albert Cohen , Sriram Krishnamoorthy , Boyana Norris , J. Ramanujam , P. Sadayappan, Parametric multi-level tiling of imperfectly nested loops, Proceedings of the 23rd international conference on Supercomputing, June 08-12, 2009, Yorktown Heights, NY, USA
|
|
|
|
|
|
|
REVIEW
"Pierre Jouvelot : Reviewer"
Parallelizing compilers use dependence analysis to detect
instructions that do not conflict in memory; these instructions are
amenable to parallel scheduling. Most of the interesting parallelism
occurs between array-manipulating instructions
more...
|