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Software transactional memory for large scale clusters
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Principles and Practice of Parallel Programming archive
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming table of contents
Salt Lake City, UT, USA
SESSION: Transactional memory II: STM implementation table of contents
Pages 247-258  
Year of Publication: 2008
ISBN:978-1-59593-795-7
Authors
Robert L. Bocchino  University of Illinois, Urbana, IL, USA
Vikram S. Adve  University of Illinois, Urbana, IL, USA
Bradford L. Chamberlain  Cray Inc., Seattle, WA, USA
Sponsors
SIGPLAN: ACM Special Interest Group on Programming Languages
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

While there has been extensive work on the design of software transactional memory (STM) for cache coherent shared memory systems, there has been no work on the design of an STM system for very large scale platforms containing potentially thousands of nodes. In this work, we present Cluster-STM, an STM designed for high performance on large-scale commodity clusters. Our design addresses several novel issues posed by this domain, including aggregating communication, managing locality, and distributing transactional metadata onto the nodes. We also re-evaluate several STM design choices previously studied for cache-coherent machines and conclude that, in some cases, different choices are appropriate on clusters. Finally, we show that our design scales well up to 512 processors. This is because on a cluster, the main barrier to STM scalability is the remote communication overhead imposed by the STM operations, and our design aggregates most of that communication with the communication of the underlying data.


REFERENCES

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Collaborative Colleagues:
Robert L. Bocchino: colleagues
Vikram S. Adve: colleagues
Bradford L. Chamberlain: colleagues