Communication bottleneck in hardware-software partitioning

ABSTRACT

The problem of hardware-software codesign for embedded systems using configurable architectures has been studied extensively in the past decade. In this work we studied the feasibility of utilizing Commercial Off-The-Shelf (COTS) FPGA systems for codesign. We partitioned the implementation of a set of benchmark applications on hardware and software and studied the performance and resource consumption in the system. The result of experiments demonstrated that the communication between the processor and the reconfigurable architecture is the major hurdle in the codesign, especially when using COTS System on Chips. It is demonstrated that although implementing algorithms in hardware can lead to enormous speedup, the communication overhead for transferring data variables between the configurable architecture and the processor can destroy all the achieved speedup. We especially showed that in COTS FPGAs this bottleneck is more restricting because of the weak communication structure between different IPs. Furthermore, analyzing the experimental results, we propose a partitioning mechanism; the evaluation results show that the achieved speedup using the proposed partitioning mechanism is between 2 to 300 based on application's data dependency

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Automatic synthesis

Additional Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Design studies

General Terms:
Design, Experimentation, Performance

Keywords:
FPGA, communication, hardware-software codesign