Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability

ABSTRACT

This paper develops a trace-based framework to enable concurrent process and FPGA architecture co-development. Based on process parameters and traces for FPGA applications, the framework calculates the chip level performance and power distribution and soft error rate (SER) with consideration of process variations and device aging. As examples to utilize the framework, the paper further applies heterogeneous gate lengths to logic and interconnects for energy reduction, and studies the interaction between device aging, process variation and SER

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

General Terms:
Design, Performance, Reliability

Keywords:
FPGA architecture, FPGA power model