| A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs |
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International Symposium on Field Programmable Gate Arrays
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Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
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Monterey, California, USA
SESSION: Simulation acceleration
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Pages 87-96
Year of Publication: 2008
ISBN:978-1-59593-934-0
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Authors
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Michael Pellauer
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Massachusetts Institute of Technology, Cambridge, MA
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Muralidaran Vijayaraghavan
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Massachusetts Institute of Technology, Cambridge, MA
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Michael Adler
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Intel Corporation, Hudson, MA
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Arvind
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Massachusetts Institute of Technology, Cambridge, MA
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Joel Emer
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Intel Corporation, Hudson, MA
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ABSTRACT
Recently there has been interest in using FPGAs as a platform for cycle-accurate performance models. We discuss how the properties of FPGAs make them a good platform to achieve a performance improvement over software models. Some metrics are developed to gain insight into the strengths and weaknesses of different simulation methodologies. This paper introduces A-Ports, a distributed, efficient simulation scheme for creating cycle-accurate performance models on FPGAs. Finally, we quantitatively demonstrate an average performance improvement of 19% using A-Ports over other FPGA-based simulation schemes
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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