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A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs
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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays table of contents
Monterey, California, USA
SESSION: Simulation acceleration table of contents
Pages 87-96  
Year of Publication: 2008
ISBN:978-1-59593-934-0
Authors
Michael Pellauer  Massachusetts Institute of Technology, Cambridge, MA
Muralidaran Vijayaraghavan  Massachusetts Institute of Technology, Cambridge, MA
Michael Adler  Intel Corporation, Hudson, MA
Arvind  Massachusetts Institute of Technology, Cambridge, MA
Joel Emer  Intel Corporation, Hudson, MA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

Recently there has been interest in using FPGAs as a platform for cycle-accurate performance models. We discuss how the properties of FPGAs make them a good platform to achieve a performance improvement over software models. Some metrics are developed to gain insight into the strengths and weaknesses of different simulation methodologies. This paper introduces A-Ports, a distributed, efficient simulation scheme for creating cycle-accurate performance models on FPGAs. Finally, we quantitatively demonstrate an average performance improvement of 19% using A-Ports over other FPGA-based simulation schemes


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Michael Pellauer: colleagues
Muralidaran Vijayaraghavan: colleagues
Michael Adler: colleagues
Arvind: colleagues
Joel Emer: colleagues