Lithographic aerial image simulation with FPGA-based hardwareacceleration

ABSTRACT

Lithography simulation, as an essential step in design for manufacturability (DFM), is still far from computationally efficient. Most leading companies use large clusters of server computers to achieve acceptable turn-around time. Thus co-processor acceleration is very attractive for obtaining increased computational performance with reduced power consumption. This paper describes an implementation of a customized accelerator on FPGA using a polygon-based simulation model. An application-specific memory partitioning scheme is designed to meet the bandwidth requirements for a large number of processing elements. Deep loop pipelining and ping-pong buffer based function block pipelining are also implemented in our design. Initial results show a 15X speedup versus the software implementation running on a microprocessor, and more speedup is expected via further performance tuning. The implementation also leverages state-of-art C-to-RTL synthesis tools. At the same time, we also identified the need for manual architecture-level exploration for parallel implementations

REFERENCES

• 1: Datasheet of calibre nmopc. Mentor Graphics.
• 2: http://impulsec.com.
• 3: http://www.autoesl.com.
• 4: http://www.xtremedatainc.com.
• 5: Y. Cao, Y.-W. Lu, L. Chen, and J. Ye. Optimized hardware and software for fast full-chip simulation. Optical Microlithography XVIII, 5754(1):407--414, 2004.
• 6: Nicolas Bailey Cobb , Avideh Zakhor, Fast optical and process proximity correction algorithms for integrated circuit manufacturing, University of California, Berkeley, 1998
• 7: M. Frigo and S.G. Johnson. The design and implementation of FFTW3. Proceedings of the IEEE, 93(2):216--231, 2005.
• 8: C.A. Mack. Lithography simulation in semiconductor manufacturing. Advanced Microlithography Technologies, 5645(1):6383, 2005.
• 9: O. Mencer and R.G. Clapp. Accelerating 2d ffts and convolutions for seismic processing. Brief Notes by Maxeler Technologies.
• 10: V. Podlozhnyuk. Fft based 2d convolution. NVIDIA white paper.
• 11: I. Uzun, A. Amira, and A. Bouridane. Fpga implementations of fast fourier transforms for real-time signal and image processing. IEE Proceedings -- Vision, Image, and Signal Processing, 152(3):283--296, 2005.
• 12: A.K.-K. Wong. Private communication. Magma Design Automation Inc.
• 13: A.K.-K. Wong. Optical imaging in projection microlithography. SPIE Press, Bellingham, WA, 2005.
• 14: M.S. Yeung. Fast and rigorous three-dimensional mask diffraction simulation using battle-lemarie wavelet-based multiresolution time-domain method. Optical Microlithography XVI, 5040(1):69--77, 2003.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Algorithms implemented in hardware

General Terms:
Algorithms, Design, Performance

Keywords:
FPGA, co-processor acceleration, lithography simulation