Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations

ABSTRACT

A new method for improving the timing yield of field-programmable gate array (FPGA) devices affected by intrinsic within-die variation is proposed. The timing variation is reduced by selecting an appropriate configuration for each chip from a set of independent configurations, the critical paths of which do not share the same circuit resources on the FPGA. In this article, the actual method used to generate independent multiple configurations by simply repeating the routing phase is shown, along with the results of Monte Carlo simulation with 10,000 samples. One simulation result showed that the standard deviations of maximum critical path delays are reduced by 28% and 49% for 10% and 30% V_th variations (σ/ μ), respectively, with 10 independent configurations. Therefore, the proposed method is especially effective for larger V_th variation and is expected to be useful for suppressing the performance variation of FPGAs due to the future increase of parameter variation. Another simulation result showed that the effectiveness of the proposed technique was saturated at the use of 10 or more configurations because of the degradation of the quality of the configurations. Therefore, the use of 10 or fewer configurations is reasonable.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Reliability

Keywords:
FPGA, configuration, timing yield, within-die variation