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ABSTRACT
Efficiently exploring exponential-size architectural design spaces with many interacting parameters remains an open problem: the sheer number of experiments required renders detailed simulation intractable. We attack this via an automated approach that builds accurate predictive models. We simulate sampled points, using results to teach our models the function describing relationships among design parameters. The models can be queried and are very fast, enabling efficient design tradeoff discovery. We validate our approach via two uniprocessor sensitivity studies, predicting IPC with only 1--2% error. In an experimental study using the approach, training on 1% of a 250-K-point CMP design space allows our models to predict performance with only 4--5% error. Our predictive modeling combines well with techniques that reduce the time taken by each simulation experiment, achieving net time savings of three-four orders of magnitude.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Bigus, J. 1994a. Applying neural networks to computer system performance tuning. In Proc. IEEE International Conference on Neural Networks.
|
| |
2
|
Bigus, J. 1994b. Computer system performance modeling using neural networks. In Proc. International Neural Network Society Conference. 510--515.
|
| |
3
|
Borkar, S., Dubey, P., Kahn, K., Kuck, D., Mulder, H., Pawlowski, S., and Rattner, J. 2006. Platform 2015: Intel processsor and platform evolution for the next decade. White Paper, Intel Corporation.
|
| |
4
|
Cai, G., Chow, K., Nakanishi, T., Hall, J., and Barany, M. 1998. Multivariate power/performance analysis for high performance mobile microprocessor design. In Power Driven Microarchitecture Workshop.
|
| |
5
|
Caruana, R., Lawrence, S., and Giles, C. 2000. Overfitting in neural nets: Backpropagation, conjugate gradient, and early stopping. In Proc. Neural Information Processing Systems Conference.
|
| |
6
|
Chow, K. and Ding, J. 1997. Multivariate analysis of Pentium Pro processor. In Intel Software Developers Conference. 84--91.
|
| |
7
|
|
| |
8
|
|
| |
9
|
Eeckhout, L., Nussbaum, S., Smith, J., and De Bosschere, K. 2003b. Statistical simulation: Adding efficiency to the computer designer's toolbox. IEEE Micro 23, 5, 26--38.
|
 |
10
|
Lieven Eeckhout , Robert H. Bell Jr. , Bastiaan Stougie , Koen De Bosschere , Lizy K. John, Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies, Proceedings of the 31st annual international symposium on Computer architecture, p.350, June 19-23, 2004, München, Germany
|
| |
11
|
|
| |
12
|
Eeckhout, L., Vandierendonck, H., and De Bosschere, K. 2003a. Quantifying the impact of input data sets on program behavior and its applications. Journal of Instruction Level Parallelism 5, http://www.jilp.org/vol5.
|
| |
13
|
|
 |
14
|
|
| |
15
|
|
| |
16
|
|
| |
17
|
Hastie, T., Tibshirani, R., and Friedman, J. 2001. The Elements of Statistical Learning: Data Mining, Inference, and Prediction. Springer Verlag, New York.
|
| |
18
|
Ipek, E., de Supinski, B., Schulz, M., and McKee, S. 2005. An approach to performance prediction for parallel applications. In Proc. ACM/IEEE Euro-Par International European Conference on Parallel Computing. 196--205.
|
 |
19
|
Engin Ïpek , Sally A. McKee , Rich Caruana , Bronis R. de Supinski , Martin Schulz, Efficiently exploring architectural design spaces via predictive modeling, Proceedings of the 12th international conference on Architectural support for programming languages and operating systems, October 21-25, 2006, San Jose, California, USA
|
| |
20
|
|
| |
21
|
|
| |
22
|
|
| |
23
|
Joseph, P., Vaswani, K., and Thazhuthaveetil, M. 2006b. Use of linear regression models for processor performance analysis. In Proc. 12th IEEE Symposium on High Performance Computer Architecture. 99--108.
|
 |
24
|
|
| |
25
|
|
| |
26
|
|
 |
27
|
|
 |
28
|
|
| |
29
|
Kunkel, S., Eickemeyer, R., Lipasti, M., Mullins, T., O'Krafka, B., Rosenberg, H., VanderWiel, S., Vitale, P., and Whitley, L. 2000. A performance methodology for commercial servers. IBM Journal of Research and Development 44, 6, 851--872.
|
 |
30
|
|
| |
31
|
Li, Y., Lee, B., Brooks, D., Hu, Z., and Skadron, K. 2006. CMP design space exploration subject to physical constraints. In Proc. 12th IEEE Symposium on High Performance Computer Architecture. 15--26.
|
| |
32
|
Martonosi, M. and Skadron, K. 2001. NSF computer performance evaluation workshop: Summary and action items. http://www.princeton.edu/~mrm/nsf_sim_final.pdf.
|
| |
33
|
Marzban, C. 2000. A neural network for tornado diagnosis. Neural Computing and Applications 9, 2, 133--141.
|
| |
34
|
|
 |
35
|
Anish Muttreja , Anand Raghunathan , Srivaths Ravi , Niraj K. Jha, Automated energy/performance macromodeling of embedded software, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
[doi> 10.1145/996566.996599]
|
 |
36
|
Anish Muttreja , Anand Raghunathan , Srivaths Ravi , Niraj K. Jha, Hybrid simulation for embedded software energy estimation, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA
[doi> 10.1145/1065579.1065590]
|
 |
37
|
|
 |
38
|
|
| |
39
|
|
| |
40
|
Pomerleau, D. 1993. Knowledge-based training of artificial neural networks for autonomous robot driving. In Robot Learning, J. Connell and S. Mahadevan, Eds. Kluwer Academic Publ., Boston, MA. 19--43.
|
| |
41
|
Ramanathan, R. 2006. Intel multi-core processors: Making the move to quad-core and beyond. White Paper, Intel Corporation.
|
| |
42
|
|
| |
43
|
Renau, J. 2002. SESC. http://sesc.sourceforge.net/index.html.
|
| |
44
|
Saar-Tsechansky, M. and Provost, F. 2001. Active learning for class probability estimation and ranking. In Proc. 17th International Joint Conference on Artificial Intelligence. 911--920.
|
 |
45
|
|
 |
46
|
|
| |
47
|
Van Biesbrouck, M., Eeckhout, L., and Calder, B. 2005. Efficient sampling startup for sampled processor simulation. In Proc. 1st International Conference on High Performance Embedded Architectures and Compilers. 47--67.
|
 |
48
|
|
| |
49
|
Wilton, S. and Jouppi, N. 1996. CACTI: An enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuits 31, 5 (May), 677--688.
|
 |
50
|
|
 |
51
|
|
| |
52
|
|
| |
53
|
Yoo, R., Lee, H., Chow, K., and Lee, H. 2006. Constructing a non-linear model with neural networks for workload characterization. In Proc. IEEE International Symposium on Workload Characterization. 150--159.
|
 |
54
|
|
|