Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays

ABSTRACT

Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we suggest a way to reduce the decoder size and keep it defect tolerant by using multiple threshold voltages (V_T), which is enabled by our underlying technology. We define two types of multi-valued decoders and model the defects they undergo due to the V_T variation. Multi-valued hot decoders yield better area saving than n-ary reflexive codes (NRC), and under severe conditions, NRC enables a non-vanishing part of the code space to recover. There are many combinations of decoder type and number of V_T's yielding equal effective memory capacities. The optimal choice saves area up to 24%. We also show that the precision of the addressing voltages for decoders with unreliable V_T's is a crucial parameter for the decoder design and permits large savings in memory area.

REFERENCES

• 1: Robert Beckman, Ezekiel Johnston-Halperin, Yi Luo, Jonathan E. Green, and James R. Heath. Bridging dimensions: Demultiplexing ultrahigh density nanowire circuits. Science, 310(5747):465--468, 2005.
• 2: Michael Butts , Andrée DeHon , Seth Copen Goldstein, Molecular electronics: devices, systems and tools for gigagate, gigabit chips, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.433-440, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774636]
• 3: G. F. Cerofolini. Realistic limits to computation. ii. the technological side. Applied Physics A, 86(1):31--42, 2007.
• 4: Y. Cui, Z. Zhong, D. Wang, W. U. Wang, and C. M. Lieber. High performance silicon nanowire field effect transistor. Nano Letters, 3(2):149--152, 2003.
• 5: A. DeHon. Array-based architecture for FET-based, nanoscale electronics. IEEE Transactions on Nanotechnology, 2(1):23--32, 2003.
• 6: André DeHon, Design of programmable interconnect for sublithographic programmable logic arrays, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA [doi>10.1145/1046192.1046210]
• 7: A. DeHon, S. C. Goldstein, P. J. Kuekes, and P. Lincoln. Nonphotolithographic nanoscale memory density prospects. IEEE transactions on Nanotechnology, 4(2):215--228, 2005.
• 8: A. DeHon, P. Lincoln, and J. E. Savage. Stochastic assembly of sublithographic nanoscale interfaces. IEEE Trans. on Nanotechnology, 2(3):165--174, 2003.
• 9: Andre DeHon , Michael J. Wilson, Nanowire-based sublithographic programmable logic arrays, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA [doi>10.1145/968280.968299]
• 10: J. Kedzierski et al. Metal-gate FINFET and fully-depleted SOI devices using total gate silicidation. In IEEE Electron Devices Meeting, pages 247--250, 2002.
• 11: K. Gopalakrishnan et al. The micro to nano addressing block. In IEEE Electron Devices Meeting, page 19.4, 2005.
• 12: S. Monfray et al. 50 nm-gate all around (GAA)-silicon on nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process. In Symposium on VLSI Technology, pages 108--109, 2002.
• 13: Seth Copen Goldstein , Mihai Budiu, NanoFabrics: spatial computing using molecular electronics, Proceedings of the 28th annual international symposium on Computer architecture, p.178-191, June 30-July 04, 2001, Göteborg, Sweden
• 14: M. S. Gudiksen, L. J. Lauhon, J. Wang, D. C. Smith, and C. M. Lieber. Growth of nanowire superlattice structures for nanoscale photonics and electronics. Nature, 415:617--620, 2002.
• 15: T. Hogg, Yong Chen, and P. J. Kuekes. Assembling nanoscale circuits with randomized connections. IEEE Transactions on Nanotechnology, 5(2):110--122, 2006.
• 16: J. D. Holmes, K. P. Johnston, R. C. Doty, and B. A. Korgel. Control of thickness and orientation of solution-grown Silicon nanowires. Science, 287(5457):1471--1473, 2000.
• 17: Yu Huang, Xiangfeng Duan, Yi Cui, Lincoln J. Lauhon, Kyoung-Ha Kim, and Charles M. Lieber. Logic gates and computation from assembled nanowire building blocks. Science, 249:1313--1317, 2001.
• 18: J. Kedzierski and J. Bokor. Fabrication of planar Silicon nanowires on Silicon-on-insulator using stress limited oxidation. Journal of Vacuum Science and Technology B, 15(6):2825--2828, 1997.
• 19: S.-M. Koo, A. Fujiwara, J.-P. Han, E. M. Vogel, C. A. Richter, and J. E. Bonevich. Inversion current in Silicon nanowire field effect transistors. Nano Letters, 4(11):2197--2201, 2004.
• 20: P. J. Kuekes and R. S. Williams. Demultiplexer for a molecular wire crossbar network (MWCN DEMUX), 2001.
• 21: Chun Ning Lau, Duncan R. Stewart, R. Stanley Williams, and Marc Bockrath. Direct observation of nanoscale switching centers in metal/molecule/metal structures. Nano Letters, 4(4):569--572, 2004.
• 22: L. J. Lauhon, M. S. Gudiksen, D. Wang, and C. M. Lieber. Epitaxial core-shell and core-multishell nanowire heterostructures. Nature, 420:57--61, 2002.
• 23: Y. Luo, C. P. Collier, J. O. Jeppesen, K. A. Nielsen, E. DeIonno, G. Ho, J. Perkins, H.-R. Tseng, T. Yamamoto, J. F. Stoddart, and J. R. Heath. Two-dimensional molecular electronics circuits. Journal of Chemical Physics and Physical Chemistry (ChemPhysChem), 3:519--525, 2002.
• 24: N. A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P. M. Petroff, and J. R. Heath. Ultrahigh-density nanowire lattices and circuits. Science, 300(5616):112--115, 2003.
• 25: K. E. Moselund, D. Bouvet, L. Tschuor, V. Pot, P. Dainesi, C. Eggimann, N. Le Thomas, R. Houdré, and A. M. Ionescu. Cointegration of gate-all-around MOSFETs and local Silicon-on-insulator optical waveguides on bulk silicon. IEEE Transactions on Nanotechnology, 6(1):118--125, 2007.
• 26: Eric Rachlin. Robust nanowire decoding, www.cs.brown.edu/publications/theses/masters/2006/eerac.pdf, 2006.
• 27: T. Rueckes, K. Kim, E. Joselevich, G. Y. Tseng, C.-L. Cheung, and C. M. Lieber. Carbon nanotube based nonvolatile random access memory for molecular computing. Science, 289:94--97, 2000.
• 28: John E. Savage , Eric Rachlin , André DeHon , Charles M. Lieber , Yue Wu, Radial addressing of nanowires, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.2 n.2, p.129-154, April 2006 [doi>10.1145/1148015.1148018]
• 29: D. R. Stewart, D. A. A. Ohlberg, P. A. Beck, Y. Chen, R. Stanley Williams, J. O. Jeppesen, K. A. Nielsen, and J. Fraser Stoddart. Molecule-independent electrical switching in Pt/organic monolayer/Ti devices. Nano Letters, 4(1):133--136, 2004.
• 30: D. Whang, S. Jin, Y. Wu, and C. M. Lieber. Large-scale hierarchical organization of nanowire arrays for integrated nanosystems. Nano Letters, 3(9):1255--1259, 2003.
• 31: H.-S. P. Wong, K. K. Chan, and Y. Taur. Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel. In IEEE Electron Devices Meeting, pages 427--430, 1997.
• 32: C. M. Lieber Y. Cui. Functional nanoscale electronic devices assembled using silicon nanowire building blocks. Science, 291(5505):851--853, 2001.