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ABSTRACT

In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in previous work. Althogh peak current and power/ground noises are minimized by signal polarities assignment, an assignment without timing information may increase the clock skew significantly. As a result, a timing-aware signal polarities assigning technique is necessary. In this paper, we propose a novel signal polarities assigning technique which can not only reduce peak current and power/ground noises simultaneously but also render the clock skew in control. The experimental result shows that the clock skew produced by our algorithm is 94% of original clock skew in average while the clock skew produced by three algorithms (Partition, MST, Matching) [5] are 235%, 272%, and 283%, respectively. Moreover, our algorithm is as efficient as the three algorithms of [5] in reducing peak current and power/ground noises.

REFERENCES

• 1: John P. Uyemura, "Introduction to VLSI Circuits and Systems," JOHN WILEY & SONS, INC.
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• 3: Predictive Technology Model, http://www-device.eecs.berkeley.edu/~ptm
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• 5: Rupak Samanta , Ganesh Venkataraman , Jiang Hu, Clock buffer polarity assignment for power noise reduction, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California [doi>10.1145/1233501.1233615]
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