Skew aware polarity assignment in clock tree

ABSTRACT

In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in previous work. Althogh peak current and power/ground noises are minimized by signal polarities assignment, an assignment without timing information may increase the clock skew significantly. As a result, a timing-aware signal polarities assigning technique is necessary. In this paper, we propose a novel signal polarities assigning technique which can not only reduce peak current and power/ground noises simultaneously but also render the clock skew in control. The experimental result shows that the clock skew produced by our algorithm is 94% of original clock skew in average while the clock skew produced by three algorithms (Partition, MST, Matching) [5] are 235%, 272%, and 283%, respectively. Moreover, our algorithm is as efficient as the three algorithms of [5] in reducing peak current and power/ground noises.

REFERENCES

• 1: John P. Uyemura, "Introduction to VLSI Circuits and Systems," JOHN WILEY & SONS, INC.
• 2: Sachin S. Sapatnekar , Haihua Su, Analysis and Optimization of Power Grids, IEEE Design & Test, v.20 n.3, p.7-15, May 2003 [doi>10.1109/MDT.2003.1198680]
• 3: Predictive Technology Model, http://www-device.eecs.berkeley.edu/~ptm
• 4: Yow-Tyng Nieh , Shih-Hsu Huang , Sheng-Yu Hsu, Minimizing peak current via opposite-phase clock tree, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065629]
• 5: Rupak Samanta , Ganesh Venkataraman , Jiang Hu, Clock buffer polarity assignment for power noise reduction, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California [doi>10.1145/1233501.1233615]
• 6: G. Venkataraman , N. Jayakumar , J. Hu , P. Li , Sunil Khatri , Anand Rajaram , P. McGuinness , C. Alpert, Practical techniques to reduce skew and its variations in buffered clock networks, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.592-596, November 06-10, 2005, San Jose, CA
• 7: Matthew R. Guthaus , Dennis Sylvester , Richard B. Brown, Clock buffer and wire sizing using sequential programming, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1147171]