| Skew aware polarity assignment in clock tree |
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International Conference on Computer Aided Design
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Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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San Jose, California
SESSION: Advances in routing and clock design
table of contents
Pages 376-379
Year of Publication: 2007
ISBN ~ ISSN:1092-3152 , 1-4244-1382-6
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IEEE Press
Piscataway, NJ, USA
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Downloads (6 Weeks): 8, Downloads (12 Months): 33, Citation Count: 1
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ABSTRACT
In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in previous work. Althogh peak current and power/ground noises are minimized by signal polarities assignment, an assignment without timing information may increase the clock skew significantly. As a result, a timing-aware signal polarities assigning technique is necessary. In this paper, we propose a novel signal polarities assigning technique which can not only reduce peak current and power/ground noises simultaneously but also render the clock skew in control. The experimental result shows that the clock skew produced by our algorithm is 94% of original clock skew in average while the clock skew produced by three algorithms (Partition, MST, Matching) [5] are 235%, 272%, and 283%, respectively. Moreover, our algorithm is as efficient as the three algorithms of [5] in reducing peak current and power/ground noises.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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John P. Uyemura, "Introduction to VLSI Circuits and Systems," JOHN WILEY & SONS, INC.
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Predictive Technology Model, http://www-device.eecs.berkeley.edu/~ptm
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G. Venkataraman , N. Jayakumar , J. Hu , P. Li , Sunil Khatri , Anand Rajaram , P. McGuinness , C. Alpert, Practical techniques to reduce skew and its variations in buffered clock networks, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.592-596, November 06-10, 2005, San Jose, CA
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