|
 ABSTRACT
This paper describes the FAST methodology that enables a single FPGA to accelerate the performance of cycle-accurate computer system simulators modeling modern, realistic SoCs, embedded systems and standard desktop/laptop/server computer systems. The methodology partitions a simulator into (i) a functional model that simulates the functionality of the computer system and (ii) a predictive model that predicts performance and other metrics. The partitioning is crafted to map most of the parallel work onto a hardware-based predictive model, eliminating much of the complexity and difficulty of simulating parallel constructs on a sequential platform. FAST conventions and libraries have been designed to make creating, modifying, using and measuring such simulators straightforward. We describe a prototype FAST system: a full-system, RTL-level cycle-accurate-capable computer system simulator that executes the x86 ISA, boots unmodified Linux and executes unmodified x86 applications. The prototype runs two to three orders of magnitude faster than the fastest Intel and AMD RTL-level cycle-accurate x86 software-based simulators and about six to seven times faster than RTL simulation.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
| |
2
|
D. A. Penry, D. Fay, D. Hodgdon, R. Wells, G. Schelle, D. I. August, and D. Connors, "Exploiting Parallelism and Structure to Accelerate the Simulation of Chip Multi-processors," in 12th International Symposium on High-Performance Computer Architecture, Feb 2006, pp. 27--38.
|
| |
3
|
D. Chiou, "FAST: FPGA-based Acceleration of Simulator Timing models," in Proceedings of the first Workshop on Architecture Research using FPGA Platforms, held in conjunction with HPCA-11, San Francisco, CA, Feb. 2005.
|
| |
4
|
D. Chiou, H. Sanjeliwala, D. Sunwoo, J. Z. Xu, and N. Patil, "FPGA-based Fast, Cycle-Accurate, Full-System Simulators," in Proceedings of the second Workshop on Architecture Research using FPGA Platforms, held in conjunction with HPCA-12, Austin, TX, Feb. 2006.
|
| |
5
|
D. Chiou, "A simulation method," United States Patent Application 11/633,657, Dec. 2006.
|
| |
6
|
"Bluespec webpage," http://www.bluespec.com.
|
| |
7
|
|
| |
8
|
"DRC Computer," http://www.drccomputer.com/.
|
| |
9
|
"SPEC webpage," http://www.spec.org.
|
 |
10
|
|
| |
11
|
Joel Emer , Pritpal Ahuja , Eric Borch , Artur Klauser , Chi-Keung Luk , Srilatha Manne , Shubhendu S. Mukherjee , Harish Patil , Steven Wallace , Nathan Binkert , Roger Espasa , Toni Juan, Asim: A Performance Model Framework, Computer, v.35 n.2, p.68-76, February 2002
[doi> 10.1109/2.982918]
|
| |
12
|
N. L. Binkert, E. G. Hallnor, and S. K. Reinhardt, "Network-Oriented Full-System Simulation using M5," in Sixth Workshop on Computer Architecture Evaluation using Commerical Workloads (CAECW), Feb. 2003.
|
| |
13
|
J. Emer, "HASim talk at RAMP Retreat, June 2007." {Online}. Available: http://ramp.eecs.berkeley.edu
|
| |
14
|
R. Bhargava, L. Barnes, and B. Sander, "personal email communication," Aug. 2007.
|
| |
15
|
L. Zhang, "personal email communication," Aug. 2007.
|
| |
16
|
J. Holt, "personal email communication," July 2007.
|
| |
17
|
|
| |
18
|
|
| |
19
|
M. T. Yourst, "PTLSim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator," in Proceedings of ISPASS, Jan. 2007.
|
| |
20
|
"VAST Systems," www.vastsystems.com.
|
| |
21
|
N. Dave, M. Pellauer, Arvind, and J. Emer, "Implementing a Functional/Timing Partitioned Microprocessor Simulator with an FPGA," in Proceedings of the Workshop on Architecture Research using FPGA Platforms, held at HPCA-12, Feb. 2006. {Online}. Available: http://www.cag.csail.mit.edu/warfp2006/submissions/dave-mit.pdf
|
| |
22
|
J. D. Davis, L. Hammond, and K. Olukotun, "A Flexible Architecture for Simulation and Testing (FAST) Multiprocessor Systems," in Proceedings of the Workshop on Architecture Research using FPGA Platforms, held at HPCA-11, Feb. 2005. {Online}. Available: http://cag.csail.mit.edu/warfp2005/submissions/33-davis.pdf
|
| |
23
|
S.-L. Lu, E. Nurvitadhi, J. Hong, and S. Larsen, "Memory Subsystem Performance Evaluation with FPGA based Emulators," in Proceedings of the Workshop on Architecture Research using FPGA Platforms, held at HPCA-11, Feb. 2005. {Online}. Available: http://cag.csail.mit.edu/warfp2005/submissions/16-lu.pdf
|
| |
24
|
C. Kozyrakis and K. Olukotun, "ATLAS: A Scalable Emulator for Transactional Parallel Systems," in Proceedings of the Workshop on Architecture Research using FPGA Platforms, held at HPCA-11, Feb. 2005. {Online}. Available: http://cag.csail.mit.edu/warfp2005/submissions/6-kozyrakis.pdf
|
| |
25
|
E. Nurvitadhi and J. Hoe, "Full-System Architectural Exploration Sandbox," in Proceedings of the Workshop on Architecture Research using FPGA Platforms, held at HPCA-11, Feb. 2005. {Online}. Available: http://cag.csail.mit.edu/warfp2005/submissions/18-nurvitadhi.pdf
|
| |
26
|
D. Patterson, Arvind, K. Asanović, D. Chiou, J. C. Hoe, C. Kozyrakis, S.-L. Lu, M. Oskin, J. Rabaey, and J. Wawrzynek, "RAMP: Research Accelerator for Multiple Processors," in Proceedings of Hot Chips 18, Palo Alto, CA, Aug. 2006.
|
| |
27
|
T. Suh, H.-H. S. Lee, S.-L. Lu, and J. Shen, "Initial Observations of Hardware/Software Co-Simulation using FPGA in Architectural Research," in Proceedings of the Workshop on Architecture Research using FPGA Platforms, held at HPCA-12, Feb. 2006. {Online}. Available: http://www.cag.csail.mit.edu/warfp2006/submissions/suh-git.pdf
|
CITED BY
|
|
Michael Pellauer , Muralidaran Vijayaraghavan , Michael Adler , Arvind , Joel Emer, A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
|
|
Adobe Acrobat
QuickTime
Windows Media Player
Real Player
Pdf