Thermal-aware Steiner routing for 3D stacked ICs

ABSTRACT

In this paper, we present the first work on the Steiner routing for 3D stacked ICs. In the 3D Steiner routing problem, the pins are located in multiple device layers, which makes it more general than its 2D counterpart. Our algorithm consists of two steps: tree construction and tree refinement. Our tree construction algorithm builds a delay-oriented Steiner tree under a given thermal profile. We show that thermal-aware 3D tree construction involves the minimization of two-variable Elmore delay function. In our tree refinement algorithm, we reposition the through-vias while preserving the original routing topology for further thermal optimization under performance constraint. We employ a novel scheme to relax the initial NLP formulation to ILP and consider all through-vias from all nets simultaneously. Our related experiments show the effectiveness of our proposed solutions.

REFERENCES

• 1: M. Yilidiz and P. H. Madded, "Preferred Direction Steiner Trees," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2002.
• 2: J. Cong , Yan Zhang, Thermal via planning for 3-D ICs, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.745-752, November 06-10, 2005, San Jose, CA
• 3: Vasilis F. Pavlidis , Eby G. Friedman, Interconnect delay minimization through interlayer via placement in 3-D ICs, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA [doi>10.1145/1057661.1057669]
• 4: A. Ajami, K. Banerjee, and M. Pedram, "Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs," in Proc. of IEEE Custom Integrated Circuits Conference, May 2001, pp. pp. 233--236.
• 5: K. Boese, A. Kahng, B. McCoyy, and G. Robins, "Near-Optimal Critical Sink Routing Tree Constructions," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 1995.
• 6: M. Pathak and S. K. Lim, "Thermal-aware Steiner Routing for 3D Stacked ICs," Georgia Institute of Technology, Tech. Rep. GIT-CERCS-07-18, 2007.
• 7: T.-Y. Wang and C. C.-P. Chen, "3-d thermal-adi: A linear-time chip level transient thermal simulator," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 1434--1445, 2002.
• 8: Brent Goplen , Sachin Sapatnekar, Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.86, November 09-13, 2003 [doi>10.1109/ICCAD.2003.60]
• 9: Jason Cong , Kwok-Shing Leung , Dian Zhou, Performance-driven interconnect design based on distributed RC delay model, Proceedings of the 30th international conference on Design automation, p.606-611, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165065]