A self-adjusting clock tree architecture to cope with temperature variations

ABSTRACT

Ensuring resilience against environmental variations is becoming one of the great challenges of chip design. In this paper, we propose a self adjusting clock tree architecture, SACTA, to improve chip performance and reliability in the presence of on-chip temperature variations. SACTA performs temperature dependent dynamic clock skew scheduling to prevent timing violations in a pipelined circuit. We present an automatic temperature adjustable skew buffer design, which enables the adaptive feature of SACTA. Furthermore, we propose an efficient and general optimization framework to determine the configuration of these special delay elements. Experimental results show that a pipeline supported by SACTA is able to prevent thermal induced timing violations within a significantly larger range of operating temperatures (enhancing the violation-free range by as much as 45°C).

REFERENCES

• 1: S. A. Bota , M. Rosales , J. L. Rosello , J. Segura , A. Keshavarzi, WITHIN DIE THERMAL GRADIENT IMPACT ON CLOCK-SKEW: ANEW TYPE OF DELAY-FAULT MECHANISM, Proceedings of the International Test Conference on International Test Conference, p.1276-1284, October 26-28, 2004
• 2: Horowitz, M., et al. Scaling, Power and the Future of CMOS. in Int. Electron Devices Meeting. 2005.
• 3: Vaibhav Nawale , Thomas W. Chen, Optimal useful clock skew scheduling in the presence of variations using robust ILP formulations, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California [doi>10.1145/1233501.1233508]
• 4: Seokwoo Lee , Shidhartha Das , Toan Pham , Todd Austin , David Blaauw , Trevor Mudge, Reducing pipeline energy demands with local DVS and dynamic retiming, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA [doi>10.1145/1013235.1013313]
• 5: John P. Fishburn, Clock Skew Optimization, IEEE Transactions on Computers, v.39 n.7, p.945-951, July 1990 [doi>10.1109/12.55696]
• 6: Deoka, R. B., et al. A Graph-Theoretic Approach to Clock Skew Optimization. in Int. Symp. on Circuits and Systems. 1994.
• 7: Friedman, E. G., Clock Distribution Networks in Synchronous Digital Integrated Circuits. Proc. of the IEEE, 2001. 89(5): p. 665--692.
• 8: Sakurai, T., et al., Alpha-Power Law MOSFET Model and Its Application to CMOS Inverter Delay and Other Formulas. IEEE Journal of Solid-State Circuits, 1990. 25: p. 584--593.
• 9: Ku, J., et al., Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits. IEEE Trans. Very Large Scale Integration Systems, 2007. 15(8).
• 10: Cao, Y., et al. New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design. in Custom Integrated Circuit Conf. 2000.
• 11: P. C. Mathias , L. M. Patnaik, Systolic Evaluation of Polynomial Expressions, IEEE Transactions on Computers, v.39 n.5, p.653-665, May 1990 [doi>10.1109/12.53578]
• 12: Chang Hoon Kim , Soonhak Kwon , Chun Pyo Hong, A fast digit-serial systolic multiplier for finite field GF(2^m), Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China [doi>10.1145/1120725.1121040]
• 13: Keiichi Iwamura , Yasunori Dohi , Hideki Imai, A Design of Reed-Solomon Decoder with Systolic-Array Structure, IEEE Transactions on Computers, v.44 n.1, p.118-122, January 1995 [doi>10.1109/12.368005]
• 14: Filanovsky, I. M., et al., Compensation of Mobility and Threshold Voltage Temperature Effects with Application in CMOS Circuits. IEEE Trans. on Circuit and Systems I, 2001. 48(7): p. 876--884.
• 15: Ravindra K. Ahuja , Thomas L. Magnanti , James B. Orlin, Network flows: theory, algorithms, and applications, Prentice-Hall, Inc., Upper Saddle River, NJ, 1993
• 16: Kevin D. Wayne, A polynomial combinatorial algorithm for generalized minimum cost flow, Proceedings of the thirty-first annual ACM symposium on Theory of computing, p.11-18, May 01-04, 1999, Atlanta, Georgia, United States [doi>10.1145/301250.301261]