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Towards high-performance flow-level packet processing on multi-core network processors
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Symposium On Architecture For Networking And Communications Systems archive
Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems table of contents
Orlando, Florida, USA
SESSION: Architecture table of contents
Pages 17-26  
Year of Publication: 2007
ISBN:978-1-59593-945-6
Authors
Yaxuan Qi  Tsinghua University & Tsinghua National Lab for Information Science and Technology
Bo Xu  Tsinghua University
Fei He  Tsinghua University
Baohua Yang  Tsinghua University
Jianming Yu  Tsinghua University
Jun Li  Tsinghua University & Tsinghua National Lab for Information Science and Technology
Sponsors
SIGARCH: ACM Special Interest Group on Computer Architecture
ACM: Association for Computing Machinery
SIGCOMM: ACM Special Interest Group on Data Communication
Publisher
ACM  New York, NY, USA
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ABSTRACT

There is a growing interest in designing high-performance network devices to perform packet processing at flow level. Applications such as stateful access control, deep inspection and flow-based load balancing all require efficient flow-level packet processing. In this paper, we present a design of high-performance flow-level packet processing system based on multi-core network processors. Main contribution of this paper includes: a) A high performance flow classification algorithm optimized for network processors; b) An efficient flow state management scheme leveraging memory hierarchy to support large number of concurrent flows; c) Two hardware-optimized order-preserving strategies that preserve internal and external per-flow packet order. Experimental results show that: a) The proposed flow classification algorithm, AggreCuts, outperforms the well-known HiCuts algorithm in terms of classification rate and memory usage; b) The presented SigHash scheme can manage over 10M concurrent flow states on the Intel IXP2850 NP with extremely low collision rate; c) The performance of internal packet order-preserving scheme using SRAM queue-array is about 70% of that of external packet order-preserving scheme realized by ordered-thread execution.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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E. J. Johnson and A. R. Kunze, "IXP2400/2850 Programming", Intel Press, 2003.
 
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Collaborative Colleagues:
Yaxuan Qi: colleagues
Bo Xu: colleagues
Fei He: colleagues
Baohua Yang: colleagues
Jianming Yu: colleagues
Jun Li: colleagues