Synthesis of a novel timing-error detection architecture

ABSTRACT

Delay variation can cause a design to fail its timing specification. Ernst et al. [2003] observe that the worst delay of a design is least probable to occur. They propose a mechanism to detect and correct occasional errors while the design can be optimized for the common cases. Their experimental results show significant performance (or power) gain as compared with the worst-case design. However, the architecture in Ernst et al. [2003] suffers the short path problem, which is difficult to resolve. In this article, we propose a novel error-detecting architecture to solve the short path problem. Our experimental results show considerable performance gain can be achieved with reasonable area overhead.

REFERENCES

• 1: Agarwal, A., Zolotov, V., and Blaauw, D. T. 2003. Statistical timing analysis using bounds and selective enumeration. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 22, 9, 1243--1260.
• 2: Aseem Agarwal , David Blaauw , Vladimir Zolotov , Sarma Vrudhula, Statistical timing analysis using bounds and selective enumeration, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA [doi>10.1145/589411.589415]
• 3: Todd M. Austin, Designing robust microarchitectures, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996591]
• 4: Sandeep Dhar , Dragan Maksimović , Bruno Kranzen, Closed-loop adaptive voltage scaling controller for standard-cell ASICs, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566437]
• 5: Dan Ernst , Nam Sung Kim , Shidhartha Das , Sanjay Pant , Rajeev Rao , Toan Pham , Conrad Ziesler , David Blaauw , Todd Austin , Krisztian Flautner , Trevor Mudge, Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.7, December 03-05, 2003
• 6: Rajamohana Hegde , Naresh R. Shanbhag, Energy-efficient signal processing via algorithmic noise-tolerance, Proceedings of the 1999 international symposium on Low power electronics and design, p.30-35, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313834]
• 7: J. A. G. Jess , K. Kalafala , S. R. Naidu , R. H. J. M. Otten , C. Visweswariah, Statistical timing for parametric yield prediction of digital integrated circuits, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.776066]
• 8: Kehl, T. 1993. Hardware self-tuning and circuit performance monitoring. In the International Conference on Computer Design (ICCD).
• 9: Liou, J. J., Krstic, A., Jiang, Y. M., and Cheng, K. T. 2003. Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 22, 6, 756--769.
• 10: Narendra V. Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Minimum padding to satisfy short path constraints, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.156-161, November 07-11, 1993, Santa Clara, California, United States
• 11: Uht, A. 2003. Uniprocessor performance enhancement through adaptive clock frequency control. In the International Conference on Advances in Infrastructure for e-Business, e-Education, e-Science, e-Medicine, and Mobile Technologies on the Internet (SSGRR).
• 12: Chandu Visweswariah, Death, taxes and failing chips, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775921]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids

General Terms:
Design

Keywords:
Logic synthesis, fault tolerance