A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques

ABSTRACT

Scan chains are popularly used as the channels for silicon testing and debugging. However, they have also been identified as one of the culprits of silicon failure more recently. To cope with this problem, several scan chain diagnosis approaches have been proposed in the past. The existing methods, however, suffer from one common drawback—that is, they rely on fault models and matching heuristics to locate the faults. Such a paradigm may run into difficulty when the fault under diagnosis does not match the fault model exactly, for example, when there is a bridging between a flip-flop and a logic cell, or the fault is temporal and only manifests itself intermittently. In light of this, we propose in this article a more versatile model-free paradigm for locating the faulty flip-flops in a scan chain, incorporating a number of signal processing techniques, such as filtering and edge detection. These techniques performed on the test responses of the failing chip under diagnosis directly can effectively reveal the fault location(s) in a scan chain. As compared to the previous works, our approach is better capable of handling intermittent faults and bridging faults, even under nonideal conditions, for example, when the core logic is also faulty. Experimental results on several real designs indicate that this approach can indeed catch some nasty faults that previous methods could not catch.

REFERENCES

• 1: Acken, J. M. and Millman, S. D. 1992. Fault model evolution for diagnosis: accuracy vs. precision. In Proceedings of IEEE Conference on Custom Integrated Circuits. 13.4.1--13.4.4.
• 2: Bhatti, N. K. and Blanton, R. D. 2006. Diagnostic test generation for arbitrary faults. In Proceedings of International Test Conference (ITC). 1--9.
• 3: R. D. (Shawn) Blanton , J. T. Chen , R. Desineni , K. N. Dwarakanath , W. Maly , T. J. Vogels, Fault Tuples in Diagnosis of Deep-Submicron Circuits, Proceedings of the 2002 IEEE International Test Conference, p.233, October 07-10, 2002
• 4: S. Edirisooriya , G. Edirisooriya, Diagnosis of scan path failures, Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), p.250, April 30-May 03, 1995
• 5: Ruifeng Guo , Srikanth Venkataraman, A technique for fault diagnosis of defects in scan chains, Proceedings of the IEEE International Test Conference 2001, p.268-277, October 30-November 01, 2001
• 6: Hsu, J.-J., Huang, S.-Y., and Tzeng, C. W. 2006. A new robust paradigm for diagnosing hold-time faults in scan chains. In Proceedings of VLSI Design, Automation, and Testing (VLSI-DAT). 171--174.
• 7: Yu Huang , Wu-Tung Cheng , Greg Crowell, Using fault model relaxation to diagnose real scan chain defects, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China [doi>10.1145/1120725.1120934]
• 8: Yu Huang , Wu-Tung Cheng , Cheng-Ju Hsieh , Huan-Yung Tseng , Alou Huang , Yu-Ting Hung, Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis, Proceedings of the conference on Design, automation and test in Europe, p.21072, February 16-20, 2004
• 9: Huang, Y., Cheng, W.-T., Hsieh, C.-J., Tseng, H.-Y., Huang, A., and Hung, Y.-T. 2003. Efficient diagnosis for multiple intermittent scan chain hold-time faults. In Proceedings of Asian Test Symposium (ATS). 44--49.
• 10: Huang, Y., Cheng, W.-T., Reddy, S.-M., Hsieh, C.-J., and Hung, Y.-T. 2003. Statistical diagnosis for intermittent scan chain hold-time fault. In Proceedings of International Test Conference (ITC). 319--328,
• 11: Kundu, S. 1993. On diagnosis of faults in a scan chain. In Proceedings of VLSI Test Symposium (VTS). 303--308.
• 12: James Chien-Mo Li, Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns*This work was supported by the National Science Council (Grant NSC 93-2220-E-002-012)., IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E88-A n.4, p.1024-1030, April 2005 [doi>10.1093/ietfec/e88-a.4.1024]
• 13: Li, J. C.-M. 2005b. Diagnosis of single stuck-at faults and multiple timing faults in scan chains. IEEE Trans. VLSI Sys. 13, 6, 708--718.
• 14: Steven D. Millman , James P. Garvey, Sr., An Accurate Bridging Fault Test Pattern Generator, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.411-418, October 26-30, 1991
• 15: Sridhar Narayanan , Ashutosh Das, An Efficient Scheme to Diagnose Scan Chains, Proceedings of the IEEE International Test Conference, p.704-713, November 03-05, 1997
• 16: Srinivas Patil , Jacob Savir, Skewed-Load Transition Test: Part 2, Coverage, Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.714-722, September 20-24, 1992
• 17: Yasuo Sato , Iwao Yamazaki , Hiroki Yamanaka , Toshio Ikeda , Masahiro Takakura, A Persistent Diagnostic Technique for Unstable Defects, Proceedings of the 2002 IEEE International Test Conference, p.242, October 07-10, 2002
• 18: Jacob Savir, Skewed-Load Transition Test: Part 1, Calculus, Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.705-713, September 20-24, 1992
• 19: Schafer, J. L. 1992. Partner SRLs for improved shift register diagnosis. In Proceedings of VLSI Test Symposium (VTS). 198--201.
• 20: Peilin Song , Franco Stellari , Alan J. Weger , Tian Xia, A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current, Proceedings of the International Test Conference on International Test Conference, p.140-147, October 26-28, 2004
• 21: Kevin Stanley, High-Accuracy Flush-and-Scan Software Diagnostic, IEEE Design & Test, v.18 n.6, p.56-62, November 2001 [doi>10.1109/54.970425]
• 22: Storey, T. M. and Maly, W. 1990.CMOS bridging fault detection. In Proceedings of International Test Conference (ITC). 842--851.
• 23: Thomas M. Storey , Wojciech Maly , John Andrews , Myron Miske, Stuck Fault and Current Testing Comparison Using CMOS Chip Test, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.311-318, October 26-30, 1991
• 24: Tzeng, C.-W. and Huang, S.-Y. 2007. Diagnosing by image recovery: finding mixed multiple timing faults in a scan chain. IEEE Trans Circ. Sys. II (Express Brief) 54, 8, 690--694.
• 25: Tzeng, C.-W., Hsu, J.-J., and Huang, S.-Y. 2007. A robust paradigm for diagnosing hold-time faults in scan chains. In IET Proceedings on Computer and Digital Techniques. Vo1. 1, 6, 706--715.
• 26: Yuejian Wu, Diagnosis of Scan Chain Failures, Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems, p.217, November 02-04, 1998
• 27: Jheng-Syun Yang , Shi-Yu Huang, Quick Scan Chain Diagnosis Using Signal Profiling, Proceedings of the 2005 International Conference on Computer Design, p.157-160, October 02-05, 2005 [doi>10.1109/ICCD.2005.89]

INDEX TERMS

Primary Classification:
  D. Software
  D.2 SOFTWARE ENGINEERING
      D.2.5 Testing and Debugging

General Terms:
Algorithms

Keywords:
Diagnosis, design for testability, fault, profiling, scan chain