| Rethinking custom ISE identification: a new processor-agnostic method |
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International Conference on Compilers, Architecture and Synthesis for Embedded Systems
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Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
table of contents
Salzburg, Austria
SESSION: Instruction-set extension
table of contents
Pages: 125 - 134
Year of Publication: 2007
ISBN:978-1-59593-826-8
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Authors
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Ajay K. Verma
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Ecole Poletechnique Federale de Lausanne (EPFL)
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Philip Brisk
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Ecole Poletechnique Federale de Lausanne (EPFL)
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Paolo Ienne
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Ecole Poletechnique Federale de Lausanne (EPFL)
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| Bibliometrics |
Downloads (6 Weeks): 5, Downloads (12 Months): 50, Citation Count: 4
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ABSTRACT
The last decade has witnessed the emergence of the Application Specific Instruction-set Processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user to augment a base processor with Instruction Set Extensions (ISEs) that execute on Application Specific Functional Units (AFUs)-dedicated hardware that executes the ISEs. Due to the limited number of read and write ports in the register file of the base processor, the size and complexity of AFUs are generally limited. Recent work has focused on overcoming these constraints by serialising access to the register file. Apart from these complications, the primary challenge in the identification and selection of the best AFU is the modelling of AFU performance in the context of different base processors: once the base processor changes, the ISE identification and AFU selection process must be re-done from scratch. Exhaustive ISE/AFU enumeration methods are not scalable and generally fail for larger applications. To address this concern, a new approach to ISE/AFU identification is proposed. In particular, we show that the speedup model of ISEs/AFUs is independent of the specific details of the base processor, under fairly reasonable assumptions. The approach presented here significantly prunes the list of best ISE/AFU candidates compared to previous approaches. Experimentally, we observe the new approach produces optimal results on larger applications where prior approaches either fail or produce inferior results.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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I. Kuon and J. Rose, "Measuring the gap between FPGAs and ASICs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-26, no.2, pp. 203--15.
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L. Pozzi, K. Atasu, and P. Ienne, Exact and approximate algorithms for the extension of embedded processor instruction sets, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-25, no. 7, pp. 1209--29, July 2006.
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Yuanqing Guo , Gerard J.M. Smit , Hajo Broersma , Paul M. Heysters, A graph covering algorithm for a coarse grain reconfigurable system, Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems, June 11-13, 2003, San Diego, California, USA
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Philip Brisk , Adam Kaplan , Ryan Kastner , Majid Sarrafzadeh, Instruction generation and regularity extraction for reconfigurable processors, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
[doi> 10.1145/581630.581672]
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CITED BY 4
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Ajay K. Verma , Philip Brisk , Paolo Ienne, Fast, quasi-optimal, and pipelined instruction-set extensions, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
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Theo Kluter , Philip Brisk , Paolo Ienne , Edoardo Charbon, Speculative DMA for architecturally visible storage in instruction set extensions, Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, October 19-24, 2008, Atlanta, GA, USA
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Paolo Bonzini , Giovanni Ansaloni , Laura Pozzi, Compiling custom instructions onto expression-grained reconfigurable architectures, Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, October 19-24, 2008, Atlanta, GA, USA
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