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Fragment cache management for dynamic binary translators in embedded systems with scratchpad
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International Conference on Compilers, Architecture and Synthesis for Embedded Systems archive
Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems table of contents
Salzburg, Austria
SESSION: Scratchpad memories table of contents
Pages: 75 - 84  
Year of Publication: 2007
ISBN:978-1-59593-826-8
Authors
Jose Baiocchi  University of Pittsburgh
Bruce R. Childers  University of Pittsburgh
Jack W. Davidson  University of Virginia
Jason D. Hiser  University of Virginia
Jonathan Misurda  University of Pittsburgh
Sponsors
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for embedded systems. However, a challenge to DBT in this domain is stringent constraints on memory and performance. The translated code buffer used by DBT may occupy too much memory space. This paper proposes novel schemes to manage this buffer with scratchpad memory. We use footprint reduction to minimize the space needed by the translated code, victim compression to reduce the cost of retranslating previously seen code, and fragment pinning to avoid evicting needed code. We comprehensively evaluate our techniques to demonstrate their effectiveness.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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A. Guha, K. Hazelwood and M. L. Soffa, "Reducing Exit Stub Memory Consumption in Code Caches", High Performance Embedded Architectures and Compilers, 2007.
 
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Intel, Intel PXA27x Processor Family, document number 280004-002, August 2004.
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Collaborative Colleagues:
Jose Baiocchi: colleagues
Bruce R. Childers: colleagues
Jack W. Davidson: colleagues
Jason D. Hiser: colleagues
Jonathan Misurda: colleagues