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Non-transparent debugging for software-pipelined loops
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International Conference on Compilers, Architecture and Synthesis for Embedded Systems archive
Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems table of contents
Salzburg, Austria
SESSION: Embedded development tools table of contents
Pages: 23 - 32  
Year of Publication: 2007
ISBN:978-1-59593-826-8
Authors
Hugo Venturini  Verimag/STMicroelectronics
Frederic Riss  STMicroelectronics
Jean-Claude Fernandez  Verimag
Miguel Santana  STMicroelectronics
Sponsors
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

This paper tackles the problem of providing correct information about program variable values in a software-pipelined loop through a non-transparent debugging approach. Since modern processors provide instruction level parallelism, software pipelining techniques have been developed to achieve better performances, especially in the context of embedded systems. Indeed, the effectiveness of software pipelining on such systems has been demonstrated both theoretically and experimentally. As it overlaps iterations and reorders statements, it also makes standard debugging information irrelevant. Hence debugging a loop which has been software-pipelined becomes very difficult. In this paper, we propose a solution relying on selected information to be generated by the compiler and an algorithm for the debugger not to mislead the user.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Hugo Venturini: colleagues
Frederic Riss: colleagues
Jean-Claude Fernandez: colleagues
Miguel Santana: colleagues