Aggressive snoop reduction for synchronized producer-consumer communication in energy-efficient embedded multi-processors

ABSTRACT

Snoop-based cache coherence protocols are typically used when multiple processor cores share memory through a common bus. It is well known, however, that these coherence protocols introduce an excessive power overhead.To help alleviate this problem, we propose an application-driven customization technique where application knowledge regarding data sharing in producer-consumer relationships is used in order to aggressively eliminate unnecessary and predictable snoop-induced cache tag lookups even for references to shared data, thus, achieving significant power reduction with minimal hardware cost. Snoop-induced cache tag lookups for accesses to both shared and private data are eliminated when it is ensured that such lookups will not result in extra knowledge regarding the cache state in respect to the other caches and memories.The proposed methodology relies on the combined support from the compiler, the operating system, and the hardware architecture. Our experiments show average power reductions of more than 80% compared to a general-purpose snoop protocol.

REFERENCES

• 1: Jim Nilsson , Anders Landin , Per Stenström, The Coherence Predictor Cache: A Resource-Efficient and Accurate Coherence Prediction Infrastructure, Proceedings of the 17th International Symposium on Parallel and Distributed Processing, p.10.1, April 22-26, 2003
• 2: Magnus Ekman , Per Stenström , Fredrik Dahlgren, TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566471]
• 3: Mirko Loghi , Martin Letis , Luca Benini , Massimo Poncino, Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA [doi>10.1145/1057661.1057728]
• 4: Andreas Moshovos , Gokhan Memik , Alok Choudhary , Babak Falsafi, JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers, Proceedings of the 7th International Symposium on High-Performance Computer Architecture, p.85, January 20-24, 2001
• 5: Andreas Moshovos, RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence, Proceedings of the 32nd annual international symposium on Computer Architecture, p.234-245, June 04-08, 2005
• 6: Thomas F. Wenisch , Stephen Somogyi , Nikolaos Hardavellas , Jangwoo Kim , Anastassia Ailamaki , Babak Falsafi, Temporal Streaming of Shared Memory, Proceedings of the 32nd annual international symposium on Computer Architecture, p.222-233, June 04-08, 2005
• 7: Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States
• 8: M. R. Guthaus , J. S. Ringenberg , D. Ernst , T. M. Austin , T. Mudge , R. B. Brown, MiBench: A free, commercially representative embedded benchmark suite, Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop, p.3-14, December 02-02, 2001 [doi>10.1109/WWC.2001.15]
• 9: Nathan L. Binkert , Ronald G. Dreslinski , Lisa R. Hsu , Kevin T. Lim , Ali G. Saidi , Steven K. Reinhardt, The M5 Simulator: Modeling Networked Systems, IEEE Micro, v.26 n.4, p.52-60, July 2006 [doi>10.1109/MM.2006.82]
• 10: D. Tarjan, S. Thoziyoor and N. Jouppi, "CACTI 4.0: An Integrated Cache Timing, Power and Area Model", Technical report, HP Laboratories Palo Alto, June 2006.
• 11: Rizwan Bashirullah , Wentai Liu , Ralph K. Cavin, Low-power design methodology for an on-chip bus with adaptive bandwidth capability, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775990]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.0 General

Additional Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS

General Terms:
Algorithms, Design, Experimentation

Keywords:
cache coherence, embedded systems, low-power multiprocessor system