| Performance modeling for early analysis of multi-core systems |
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International Conference on Hardware Software Codesign
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Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
table of contents
Salzburg, Austria
SESSION: Practical approaches to system-level performance analysis
table of contents
Pages: 209 - 214
Year of Publication: 2007
ISBN:978-1-59593-824-4
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Authors
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Reinaldo Bergamaschi
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IBM T. J. Watson Research Center, Yorktown Heights, NY
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Indira Nair
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IBM T. J. Watson Research Center, Yorktown Heights, NY
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Gero Dittmann
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IBM T. J. Watson Research Center, Yorktown Heights, NY
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Hiren Patel
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Virginia Polytechnic Institute and State University, Blacksburg, VA
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Geert Janssen
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IBM T. J. Watson Research Center, Yorktown Heights, NY
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Nagu Dhanwada
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IBM STG/EDA, East Fishkill, NY
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Alper Buyuktosunoglu
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IBM T. J. Watson Research Center, Yorktown Heights, NY
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Emrah Acar
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IBM Austin Research Lab., Austin, TX
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Gi-Joon Nam
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IBM Austin Research Lab., Austin, TX
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Dorothy Kucar
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IBM T. J. Watson Research Center, Yorktown Heights, NY
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Pradip Bose
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IBM T. J. Watson Research Center, Yorktown Heights, NY
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John Darringer
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IBM T. J. Watson Research Center, Yorktown Heights, NY
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Guoling Han
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University of California, Los Angeles, CA
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Downloads (6 Weeks): 26, Downloads (12 Months): 166, Citation Count: 1
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ABSTRACT
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems, including multiple cores, caches and busses, this problem is compounded by complex performance interactions between cores, caches and interconnections, as well as by tight interdependencies between performance, power and physical characteristics of the design (i.e., floorplan). Although there are many point tools for the analysis of performance, or power, or floorplan of complex systems-on-chip (SoCs), there are surprisingly few works on an integrated tool that is capable of analyzing these various system characteristics simultaneously and allow the user to explore different design configurations and their effect on performance, power, size and thermal aspects. This paper describes an integrated tool for early analysis of performance, power, physical and thermal characteristics of multi-core systems. It includes cycle-accurate, transaction-level SystemC-based performance models of POWER processors and system components (i.e., caches, buses). Power models, for power computation, physical models for floorplanning and packaging models for thermal analysis are also included. The tool allows the user to build different systems by selecting components from a library and connecting them together in a visual environment. Using these models, users can simulate and dynamically analyze the performance, power and thermal aspects of multi-core systems.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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S.R. Kunkel, R.J. Eickemeyer, M.H. Lipasti, T.J. Mullins, B. O'Krafka, H. Rosenberg, S.P. VanderWiel, P.L. Vitale, and L.D. Whitley, "A performance methodology for commercial servers". IBM Journal of Research & Development, Vol.44, No.6, November, 2000.
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D. Brooks , P. Bose , V. Srinivasan , M. K. Gschwind , P. G. Emma , M. G. Rosenfield, New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors, IBM Journal of Research and Development, v.47 n.5-6, p.653-670, September 2003
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Open Access Initiative, www.si2.org.
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J. Tendler, J.S. Dodson, J.S. Fields Jr., H. Le, and B. Sinharoy, "POWER4 system microarchitecture". IBM Journal of Research & Development, Vol.46, No.1, January, 2002.
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SPEC Standard Performance Evaluation Corporation, www.spec.org.
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CITED BY
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Reinaldo Bergamaschi , Guoling Han , Alper Buyuktosunoglu , Hiren Patel , Indira Nair , Gero Dittmann , Geert Janssen , Nagu Dhanwada , Zhigang Hu , Pradip Bose , John Darringer, Exploring power management in multi-core systems, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
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