ACM Home Page
Please provide us with feedback. Feedback
Optimizing indirect branch prediction accuracy in virtual machine interpreters
Full text PdfPdf (716 KB)
Source
ACM Transactions on Programming Languages and Systems (TOPLAS) archive
Volume 29 ,  Issue 6  (October 2007) table of contents
Article No. 37  
Year of Publication: 2007
ISSN:0164-0925
Authors
Kevin Casey  Trinity College Dublin, Dublin, Ireland
M. Anton Ertl  TU Wien
David Gregg  Trinity College Dublin, Dublin, Ireland
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 54,   Downloads (12 Months): 178,   Citation Count: 1
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1286821.1286828
What is a DOI?

ABSTRACT

Interpreters designed for efficiency execute a huge number of indirect branches and can spend more than half of the execution time in indirect branch mispredictions. Branch target buffers (BTBs) are the most widely available form of indirect branch prediction; however, their prediction accuracy for existing interpreters is only 2%--50%. In this article we investigate two methods for improving the prediction accuracy of BTBs for interpreters: replicating virtual machine (VM) instructions and combining sequences of VM instructions into superinstructions. We investigate static (interpreter build-time) and dynamic (interpreter runtime) variants of these techniques and compare them and several combinations of these techniques. To show their generality, we have implemented these optimizations in VMs for both Java and Forth. These techniques can eliminate nearly all of the dispatch branch mispredictions, and have other benefits, resulting in speedups by a factor of up to 4.55 over efficient threaded-code interpreters, and speedups by a factor of up to 1.34 over techniques relying on dynamic superinstructions alone.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
 
2
 
3
4
 
5
Casey, K., Ertl, A., and Gregg, D. 2005. Optimizations for a Java interpreter using instruction set enhancement. Tech. rep. TCD-CS-2005-61, Department of Computer Science, University of Dublin, Trinity College, Dublin, Ireland.
 
6
Casey, K., Gregg, D., and Ertl, A. 2005. Tiger---an interpreter generation tool. In International Conference on Compiler Construction (CC'05). Lecture Notes in Computer Science, vol. 3443. Springer Verlag, 246--249.
 
7
Casey, K., Gregg, D., Ertl, M. A., and Nisbet, A. 2003. Towards superinstructions for Java interpeters. In Proceedings of the 7th International Workshoop on Software and Compilers for Embedded Systems (SCOPES'03), A. Krall, Ed. Lecture Notes in Computer Science, Vol. 2826. 329--343.
8
 
9
10
11
 
12
Ertl, M. A. and Gregg, D. 2003b. The structure and performance of Efficient interpreters. J. Instruc.-Lev. Paral. 5. http://www.jilp.org/vol5/.
 
13
Ertl, M. A. and Gregg, D. 2006. Optimizing Interpreters for Processors with Branch Target Buffers. Tech. rep. TCD-CS-2006-51, Department of Computer Science, University of Dublin, Trinity College, Dublin, Ireland.
 
14
 
15
Ertl, M. A., Thalinger, C., and Krall, A. 2006. Superinstructions and replication in the Cacao JVM interpreter. J. .Net Techn. 4, 1, 31--38.
 
16
 
17
Gagnon, E. and Hendren, L. J. 2003. Effective inline-threaded interpretation of Java bytecode using preparation sequences. In Proceedings of Compiler Construction, 12th International Conference (CC'03). The Joint European Conferences on Theory and Practice of Software, ETAPS'03. 170--184.
 
18
 
19
Gochman, S., Ronen, R., Anati, I., Berkovits, A., Kurts, T., Naveh, A., Saeed, A., Sperber, Z., and Valentine, R. 2003. The Intel Pentium M processor: microarchitecture and performance. Intel Tech. J. 7, 2, 20--36.
 
20
 
21
 
22
Kaeli, D. R. and Emma, P. G. 1994. Case block table for holding multi-way branches. US Patent No. 5,333,283.
 
23
 
24
Kalamatianos, J. and Kaeli, D. 1999. Indirect branch prediction using data compression techniques. J. Instruc. Lev. Paral.
25
26
27
28
29
 
30
Rossi, M. and Sivalingam, K. 1996. A survey of instruction dispatch techniques for byte-code interpreters. Tech. rep. TKO-C79, Faculty of Information Technology, Helsinki University of Technology.
 
31
 
32
 
33
Sun-Microsystems. 2001. The Java Hotspot virtual machine. Tech. rep., Sun Microsystems Inc.
34
35
36


Collaborative Colleagues:
Kevin Casey: colleagues
M. Anton Ertl: colleagues
David Gregg: colleagues