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ABSTRACT

This work proposes the use of analog majority gates to implement combinational circuits that are intrinsically tolerant to long duration transient faults predicted for future technologies. The reasoning behind that prediction is explained, a new type of voter circuit, that uses some knowledge from the analog design arena, to implement majority gates is reviewed, and a new mapping approach to implement circuits using networks of majority gates is proposed. The implementation and validation of an adder circuit, using TMR with an analog voter and the proposed solution are analyzed, in order to confirm that the technique is indeed fault tolerant, and has advantages in terms of area and performance when compared to TMR.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Design, Reliability

Keywords:
long duration transient faults, majority logic