Viability of analog inner product operations in CMOS imagers

ABSTRACT

A new model for the sensitivity analysis of inner products to CMOS analog hardware implementation is proposed. It is derived from Spice simulations of the circuits to be implemented, and is required for the design of analog image compression systems based on vector quantization at the focal plane of CMOS imaging sensors. The model is shown to be equivalent to a simpler, previously introduced model, if the errors caused by the fabrication process are around 6%. For 1.5% errors, the results differ from the theoretical predictions made by the previous model. Image compression results and the layout of the fabricated circuit, currently under test, are presented.

REFERENCES

• 1: Jose Gabriel Rodriguez Carneiro Gomes , Sanjit K. Mitra, Mixed-signal multilayer perceptron implementation of low-complexity vector quantizers for image compression, University of California, Santa Barbara, 2004
• 2: G. Linan-Cembrano, A. Rodriguez-Vazquez, R. Carmona-Galan, F. Jimenez-Garrido, S. Espejo, and R. Dominguez-Castro. A 1000 FPS at 128x128 vision processor with 8-bit digitized I/O. IEEE J. Solid-State Circuits, 39(7), July 2004.
• 3: X. Zeng and D. S. Yeung. Sensitivity analysis of multilayer perceptron to input and weight perturbations. IEEE Trans. Neural Networks, 12(6):1358--1366, November 2001.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Algorithms implemented in hardware

Additional Classification:
  I. Computing Methodologies
  I.4 IMAGE PROCESSING AND COMPUTER VISION
      I.4.1 Digitization and Image Capture
          Subjects: Quantization

General Terms:
Design

Keywords:
CMOS analog hardware, analog image processing, vector quantization