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Soft-well digital circuit design
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Proceedings of the 20th annual conference on Integrated circuits and systems design table of contents
Copacabana, Rio de Janeiro
SESSION: Device modeling and simulation - part 1 table of contents
Pages: 196 - 201  
Year of Publication: 2007
ISBN:978-1-59593-816-9
Authors
Jens Petter Abrahamsen  University of Oslo, Oslo, Norway
Tor Sverre Lande  University of Oslo, Oslo, Norway
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper we present a novel digital design technique called soft-well circuit design improving digital circuits in fine-pitch technology. Improved noise immunity, higher-speed and reduced static power leakage may be traded for somewhat increased silicon area. The importance of soft-well design may increase in future technology where leakage and noise immunity is expected to severely impact circuit performance.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Shih-Fen Huang; Wann, C.; Yu-Shyang Huang; Chih-Yung Lin; Schafbauer, T.; Shui-Ming Cheng; Yao-Ching Cheng; Vietzke, D.; Eller, M.; Chuan Lin; Quiyi Ye; Rovedo, N.; Biesemans, S.; Nguyen, P.; Dennard, R.; Bomy Chen. Scalability and biasing strategy for CMOS with active well bias. VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on 12-14 June 2001 Page(s):107--108.
 
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Collaborative Colleagues:
Jens Petter Abrahamsen: colleagues
Tor Sverre Lande: colleagues