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A reconfigurable platform for multi-service edge routers
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Proceedings of the 20th annual conference on Integrated circuits and systems design table of contents
Copacabana, Rio de Janeiro
SESSION: Reconfigurable logic and FPGAs - part 2 table of contents
Pages: 165 - 170  
Year of Publication: 2007
ISBN:978-1-59593-816-9
Authors
Christoforos Kachris  Delft University of Technology, Delft, Netherlands
Stamatis Vassiliadis  Delft University of Technology, Delft, Netherlands
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

A main feature of current FPGAs is that they can be dynamically reconfigured to meet the network traffic requirements. In this paper we present a case study for a multi-service edge router in which the number of processors and co-processors is dynamically reconfigured to meet the network traffic workload. The system targets the Xilinx Virtex4 FPGA platform and uses the MicroBlaze soft processors for header processing and hardware acceleration units for payload processing. Furthermore, two schemes are compared for the reconfiguration of the system. The first one has fast response time but is prone to network burst traffic while the second one has slower response time but is more robust to burst traffic. The performance evaluation shows that the reconfigurable platform can achieve up to 1.5x speedup compared to a static system.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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R. Warden, Design Considerations for Edge Router, Online article, www.commsdesign.com, 8 May 2002
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J. Foag, R. Koch, Architecture Conception of a Reconfigurable Network Coprocessor Platform (DynaCore) for Flexible Task Offloading, in Proceedings of the Advanced Networking and Communications Hardware Workshop (ANCHOR 2004), Munich, June 2004
 
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K. Papademetriou, A. Dollas, Performance Evaluation of a Preloading Model in Dynamically Reconfigurable Processors, in Proceedings of the IEEE International Conference on Field Programmable Logic and Applications (FPL'06), Madrid, Spain, August 2006
 
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Basic DES Crypto Core, OpenCores, www.opencores.com

Collaborative Colleagues:
Christoforos Kachris: colleagues
Stamatis Vassiliadis: colleagues