Design of a digital FM demodulator based on a 2nd° order all-digital phase-locked loop

ABSTRACT

A software-defined radio (SDR) is a wireless communication device in which all of the signal processing is implemented in software. By simply downloading a new program, a SDR is able to interoperate with different wireless protocols, incorporate new services, and upgrade to new standards. Therefore, FPGAs have been used extensively for implementing essential functions in SDR architectures. In this paper, we explore the design of a Digital FM Receiver using the approach of an All-Digital Phase Locked-Loop (ADPLL). The digital FM Receiver circuit is designed using pure VHDL, then simulated and synthesized using ModelSim SE 6 and Leonardo Spectrum Level 3, respectively. The final circuit operates at a frequency up to 150MHz and occupies the area around 15K logic gates.

REFERENCES

• 1: Mitola, The Software Radio Architecture, IEEE Communications Magazine, May 1995, pp. 26--38.
• 2: Huie, J; D'Antonio, P; Pelt, R; Jentz, B Synthesizing FPGA Cores for Software Defined Radio General Dynamics Decision Systems. 2003 Software Defined Radio Technical Conference and Product Exposition November 17-19, 2003-Orlando, Florida.
• 3: de Fermin, R.; Perez, D.; Reguero, F. The use of VHDL for the whole design flow of digital radio devices Radio Relay Systems, 1993., Fourth European Conference on, Vol., Iss., 11-14 Oct 1993 Pages:334--337.
• 4: J. McCloskey, 4.4: Application of VHDL to Software Radio Technology, Proceedings of the International Verilog HDL Conference and VHDL International Users Forum, p.90, March 16-19, 1998
• 5: M. Rice , C. Dick , F. Harris, Maximum likelihood carrier phase synchronization in FPGA-based software defined radios, Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference, p.889-892, May 07-11, 2001 [doi>10.1109/ICASSP.2001.941058]
• 6: B. S. Song, A narrow-band CMOS FM receiver based on single sideband modulation IF filtering, IEEE J. Solid-State Circuits, vol. SC-22, pp. 1147--1154, Dec. 1987.
• 7: T. Okanobu, H. Tomiyama, and H. Arimoto, Advanced low voltage single chip radio IC, IEEE Trans. Consumer Electron., vol. 38, pp. 465--475, Aug. 1992.
• 8: M. Pardoen, J. Gerrits, and V. von Kaenel, A 0.9 V 1.2 mA 200 MHz BiCMOS single-chip narrow-band FM receiver, in Dig. IEEE Int. Solid-State Circuits Conf., Feb. 1996, pp. 348--349.
• 9: Sempel and H. Van Nieuwenburg, A fully-integrated HIFI PLL FM demodulator, in Dig. IEEE Int. Solid-State Circuits Conf., Feb. 1990, pp. 102--103.
• 10: M. Hagiwara and M. Nakagawa, Digital signal processing type stereo FM receiver, IEEE Trans. Consumer Electron., vol. CE-32, pp. 37--43, Feb. 1986.
• 11: N. Boutin, An arctangent type wideband PM/FM demodulator with improved performance, IEEE Trans. Consumer Electron., vol. 38, pp. 5-9, Feb. 1992.
• 12: Staszewski, R.B.; Chih-Ming Hung; Maggio, K.; Wallberg, J.; Leipold, D.; Balsara, P.T., All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13/spl mu/m CMOS, Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International Volume , Issue , 15-19 Feb. 2004 Page(s): 272--527
• 13: Staszewski, et al. All-digital PLL and transmitter for mobile phones Solid-State Circuits, IEEE Journal of, Vol.40, Iss.12, Dec. 2005 Pages: 2469--2482
• 14: Muhammad, et al. The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process Solid-State Circuits, IEEE Journal of, Vol.41, Iss.8, Aug. 2006 Pages: 1772-- 1783.
• 15: C.-C. Chung & C.-Y. Lee, An all-digital phase-locked loop for high-speed clock generation, IEEE J. Solid-State Circuits, 38(2), 2003, 347--351.
• 16: T.Y. Hsu, B.J. Shieh, and C.Y. Lee, An ADPLL-based Clock Recovery Circuit, Solid-State Circuits, IEEE Journal of Volume 34, Issue 8, Aug 1999 Page(s):1063--1073.
• 17: Holmes, J.; Tegnelia, C. A Second-Order All-Digital Phase-Locked Loop Communications, IEEE Transactions on {legacy, pre-1988}, Vol.22, Iss.1, Jan 1974 Pages: 62--68.
• 18: G. Pasternack and R. L. Whalin, Analysis and synthesis of a digital phase-locked loop for FM demodulation, Bell Syst. Tech. J . vol. 47, pp. 2207--2237, Dec 1968.
• 19: Kelly, C.; Gupta, S. The Digital Phase-Locked Loop as a Near-Optimum FM Demodulator Communications, IEEE Transactions on {legacy, pre-1988}, Vol.20, Iss.3, Jun 1972. Pages: 406--411.
• 20: Best R. E., Phase-Locked Loops Design, Simulation, and Applications, 5° Edition, McGraw-Hill, 2003.
• 21: Donald R. Stephens, Phase-Locked Loops for Wireless Communications: Digital and Analog Implementation, Kluwer Academic Publishers, Norwell, MA, 1998
• 22: Katsuhiko Ogata, Modern control engineering (3rd ed.), Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
• 23: John G. Proakis , Dimitris K. Manolakis, Digital Signal Processing (4th Edition), Prentice-Hall, Inc., Upper Saddle River, NJ, 2006
• 24: Alok Sinha, Linear Systems, CRC Press, Inc., Boca Raton, FL, 2007

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.1 Data Communications Devices
          Subjects: Receivers (e.g., voice, data, image)

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Simulation; Optimization; Verification

General Terms:
Design, Languages, Performance

Keywords:
FPGA, VHDL, all-digital phase-locked loop (ADPLL), digital FM demodulator, frequency modulation (FM), reconfigurable logic, software-defined radio (SDR)