Phase-aware adaptive hardware selection for power-efficient scientific computations

ABSTRACT

Increased power consumption and heat dissipation have become the major limiters of available computational resources at many high performance computing (HPC) centers. Applications that run at suchcenters typically operate in single user mode, run for longperiods of time, and have long lasting application phases. Their users are interested in obtaining the maximum performance. We propose a phase aware adaptive hardware selection technique,featuring data prefetchers and dynamic voltage and frequency scaling. Ourtechnique takes advantage of memory bound phases in scientific codes, resulting in significant power (39%) and energy (37%) reductions while maintainingor exceeding the performance of an unoptimized system.

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Design studies

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Adaptable architectures

General Terms:
Design, Experimentation, Performance

Keywords:
DVFS adaptive architecture prefetchers sparse scientific codes performance power energy