A low power multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG for mobile devices

ABSTRACT

We present a low power multimedia SoC with fully programmable 3D graphics, MPEG4 codec, H.264 decoder and JPEG codec for mobile devices. The unified shader in 3D graphics engine provides fully programmable 3D graphics with 35% area and 28% power reduction. Logarithmic lighting engine and the specialized lighting instruction enable 9.1Mvertices/s vertex throughput. The merged JPEG/MPEG4 codec and the unified shader reduce the silicon area further and the SoC consumes 6.4mm x 6.4mm in 0.13μm CMOS logic process.

REFERENCES

• 1: J.H. Sohn, et. al., "Low Power 3D Graphics Processors for Mobile Terminals", IEEE Communication Magazine, Dec. 2005
• 2: T.M. Liu, et al., "A 125W, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications", ISSCC Digest of Technology papers, pp. 402--403, 2006
• 3: R. Woo, et al., "A 210mW Graphics LSI Implementing Full 3D Pipeline with 264Mtexels/s Texturing for Mobile Multimedia Applications", ISSCC Digest of Technology Papers, pp. 44--45, 2003
• 4: J.H Sohn, et al., "A 155-mW 50-Mvertices/s Graphics Processor With Fixed-Point Programmable Vertex Shader for Mobile Applications", IEEE Journal of Solid State Circuits, Vol 41, No. 5, pp.1081--1091, May, 2006
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• 6: H. Kim, et al., "A 231MHz, 2.18mW 32bit Logarithmic Arithmetic Unit for Fixed-Point 3D Graphics System", IEEE Journal of Solid-State Circuits, Vol 41, NO. 11, pp2373--2381, November, 2006
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INDEX TERMS

Primary Classification:
  I. Computing Methodologies
  I.3 COMPUTER GRAPHICS
      I.3.1 Hardware architecture
          Subjects: Graphics processors

General Terms:
Algorithms, Design, Performance

Keywords:
low power design, mobile multimedia SoC, programmable 3D graphics