Minimizing power dissipation during write operation to register files

ABSTRACT

This paper presents a power reduction mechanism for the write operation in register files (RegFiles), which adds a conditional charge-sharing structure to the pair of complementary bit-lines in each column of the RegFile. Because the read and write ports for the RegFile are separately implemented, it is possible to avoid pre-charging the bit-line pair for consecutive writes. More precisely, when writing same values to some cells in the same column of the RegFile, it is possible to eliminate energy consumption due to precharging of the bit-line pair. At the same time, when writing opposite values to some cells in the same column of the RegFile, it is possible to reduce energy consumed in charging the bit-line pair thanks to charge-sharing. Motivated by these observations, we modify the bit-line structure of the write ports in the RegFile such that i) we remove per-cycle bitline pre-charging and ii) we employ conditional data dependent charge-sharing. Experimental results on a set of SPEC2000INT / MediaBench benchmarks show an average of 61.5% energy savings with 5.1% area overhead and 16.2% increase in write access delay.

REFERENCES

• 1: J-H. Kim et al., "Fixed-Load Energy Recovery Memory for Low Power," Proc. of IEEE Computer Society Annual Symposium on VLSI Emerging Trends in VLSI System Design, pp. 145--150, Feb. 2004.
• 2: Joohee Kim , Marios C. Papaefthymiou, Constant-load energy recovery memory for efficient high-speed operation, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA [doi>10.1145/1013235.1013296]
• 3: B-D. Yang et al., "A Low-Power ROM Using Charge Recycling and Charge Sharing Techniques," IEEE Journal of Solid-State Circuits, vol. 38, no. 4, pp. 641--653, Apr. 2003.
• 4: K. W. Mai et al., "Low-Power SRAM Design Using Half-Swing Pulse-modulation Techniques," IEEE Journal of Solid-State Circuits, vol. 33, no. 11. pp. 1659--1671, 1998.
• 5: Byung-Do Yang , Lee-Sup Kim, A low-power charge-recycling ROM architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.590-598, August 2003 [doi>10.1109/TVLSI.2003.816138]
• 6: K. Kanda et al., "90% Write Power-Saving SRAM Using Sense-Amplifying Memory Cell," IEEE Journal of Solid State Circuits, vol. 39, no. 6, pp. 46--47, Jun. 2004.
• 7: Shin-Pao Cheng , Shi-Yu Huang, A Low-Power SRAM Design Using Quiet-Bitline Architecture, Proceedings of the 2005 IEEE International Workshop on Memory Technology, Design, and Testing, p.135-139, August 03-05, 2005 [doi>10.1109/MTDT.2005.10]
• 8: Ashish Karandikar, Low Power SRAM Design using Hierarchical Divided Bit-Line Approach, Proceedings of the International Conference on Computer Design, p.82, October 05-05, 1998
• 9: Byung-Do Yang , Lee-Sup Kim, A low-power ROM using single charge-sharing capacitor and hierarchical bit line, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.4, p.313-322, April 2006 [doi>10.1109/TVLSI.2006.874303]
• 10: Ehsan Pakbaznia , Farzan Fallah , Massoud Pedram, Charge recycling in MTCMOS circuits: concept and analysis, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1146940]
• 11: http://www.eas.asu.edu/~ptm/
• 12: http://www.simplescalar.com
• 13: http://www.spec.org
• 14: Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Design, Management

Keywords:
power, register file, write operation