Voltage- and ABB-island optimization in high level synthesis

ABSTRACT

Using our framework supporting simultaneous behavioral to RTL synthesis, component-wise floorplanning, as well as ABB (adaptive body biasing) and VDD aware power and delay prediction, we present a performance neutral methodology for optimal VDD-island generation and multiple ABB application. We show that tuning supply and body voltage for the entire design reduces the total energy dissipation by 4.6-38.1% without any performance loss. By allowing more than one body voltage and without optimizing the floorplan, the savings do not rise any further. Carefully floorplanning the design, we can additionally use VDD-islands reducing the power by 8.7-49.2%. In addition to the power savings, the power and delay variability due to PTV (process, temperature, voltage) variation can be reduced with all proposed ABB approaches, assuming that only the chip structure has to be fixed at design time, but the voltage levels can be adapted after the system manufacturing.

REFERENCES

• 1: Maurice Meijer , Francesco Pessolano , Jose Pineda de Gyvez, Technology exploration for adaptive power and frequency scaling in 90nm CMOS, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA [doi>10.1145/1013235.1013245]
• 2: Ali Keshavarzi , James W. Tschanz , Siva Narendra , Vivek De , W. Robert Daasch , Kaushik Roy , Manoj Sachdev , Charles F. Hawkins, Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits, IEEE Design & Test, v.19 n.5, p.36-43, September 2002 [doi>10.1109/MDT.2002.1033790]
• 3: James W. Tschanz, James T. Kao, Siva G. Narendra, Raj Nair, Dimitri A. Antoniadis, Anantha P. Chandrakasan, Vivek De: Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage. IEEE Journal of Solid State Circuits 37(11): 2002
• 4: Cassondra Neau , Kaushik Roy, Optimal body bias selection for leakage improvement and process compensation over different technology generations, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871537]
• 5: Seongsoo Lee, Seungjun Lee, Takayasu Sakurai: Energy-Constrained VDD Hopping Scheme with Run-Time Power Estimation for Low-Power Real-Time VLSI Systems. Journal of Circuits, Systems, and Computers 11(6): 2002
• 6: Le Yan, Jiong Luo, Niraj K. Jha: Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 2005
• 7: A. Stammermann , D. Helms , M. Schulte , A. Schulz , W. Nebel, Binding, Allocation and Floorplanning in Low Power High-Level Synthesis, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.544, November 09-13, 2003 [doi>10.1109/ICCAD.2003.40]
• 8: D. Helms , Eike Schmidt , Arne Schulz , Ansgar Stammermann , Wolfgang Nebel, An Improved Power Macro-Model for Arithmetic Datapath Components, Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, p.16-24, September 11-13, 2002
• 9: Domenik Helms, Marko Hoyer, Wolfgang Nebel: Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage. PATMOS: 2006
• 10: Marko Hoyer, Domenik Helms, Wolfgang Nebel: Modeling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components. PATMOS: 2007
• 11: Siva G. Narendra, Challenges and design choices in nanoscale CMOS, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.1 n.1, p.7-49, April 2005 [doi>10.1145/1063803.1063805]
• 12: D. F. Wong , C. L. Liu, A new algorithm for floorplan design, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.101-107, July 1986, Las Vegas, Nevada, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Design

Keywords:
adaptive body biasing, leakage, process variation, voltage islands