RiceNIC: a reconfigurable network interface for experimental research and education

ABSTRACT

The evaluation of new network server architectures is usually performed experimentally using either a simulator or a hardware prototype. Accurate simulation of the hardware-software interface within the network subsystem is challenging due to the interactions of multiple asynchronous systems. Small timing inaccuracies in such a system can perturb the hardware and software state yielding potentially misleading results. Hardware prototypes show more promise because they are real-world implementations, not simplifications. Existing Ethernet network interface cards (NICs) are unsuitable for prototyping as they lack the capability and/or flexibility for advanced networking research.

RiceNIC is an open network interface prototyping platform for public use. This reconfigurable and programmable Gigabit Ethernet NIC is designed to address the dilemma of how to accurately evaluate new ideas in network server architecture, and is built for use in experimental research and education. The flexibility and capability of RiceNIC has proven invaluable in recent research efforts.

REFERENCES

• 1: Alteon Networks. Tigon/PCI Ethernet Controller, August 1997. Revision 1.04.
• 2: Todd Austin , Eric Larson , Dan Ernst, SimpleScalar: An Infrastructure for Computer System Modeling, Computer, v.35 n.2, p.59-67, February 2002 [doi>10.1109/2.982917]
• 3: Nathan L. Binkert , Ronald G. Dreslinski , Lisa R. Hsu , Kevin T. Lim , Ali G. Saidi , Steven K. Reinhardt, The M5 Simulator: Modeling Networked Systems, IEEE Micro, v.26 n.4, p.52-60, July 2006 [doi>10.1109/MM.2006.82]
• 4: Martin Casado , Greg Watson , Nick McKeown, Reconfigurable Networking Hardware: A Classroom Tool, Proceedings of the 13th Symposium on High Performance Interconnects, p.151-157, August 17-19, 2005 [doi>10.1109/CONECT.2005.32]
• 5: Rajagopalan Desikan , Doug Burger , Stephen W. Keckler, Measuring Experimental Error in Microprocessor Simulation, Proceedings of the 28th annual international symposium on Computer architecture, p.266-277, June 30-July 04, 2001, Göteborg, Sweden [doi>10.1145/379240.565338]
• 6: Jeff Gibson , Robert Kunz , David Ofelt , Mark Horowitz , John Hennessy , Mark Heinrich, FLASH vs. (Simulated) FLASH: closing the simulation loop, Proceedings of the ninth international conference on Architectural support for programming languages and operating systems, p.49-58, November 2000, Cambridge, Massachusetts, United States
• 7: L. Hsu, A. Saidi, N. Binkert, and S. Reinhardt. Sampling and stability in TCP/IP workloads. In Proceedings of the Workshop on Modeling, Benchmarking, and Simulation, June 2005.
• 8: Hyong-youb Kim , Vijay S. Pai , Scott Rixner, Increasing web server throughput with network interface data caching, Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, October 05-09, 2002, San Jose, California
• 9: Hyong-youb Kim , Vijay S. Pai , Scott Rixner, Exploiting task-level concurrency in a programmable network interface, Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming, June 11-13, 2003, San Diego, California, USA
• 10: Hyong-youb Kim , Scott Rixner, Connection handoff policies for TCP offload network interfaces, Proceedings of the 7th USENIX Symposium on Operating Systems Design and Implementation, p.21-21, November 06-08, 2006, Seattle, WA
• 11: Hyong-youb Kim , Scott Rixner, TCP offload through connection handoff, Proceedings of the 1st ACM SIGOPS/EuroSys European Conference on Computer Systems 2006, April 18-21, 2006, Leuven, Belgium
• 12: Hyong-youb Kim , Scott Rixner , Vijay S. Pai, Network Interface Data Caching, IEEE Transactions on Computers, v.54 n.11, p.1394-1408, November 2005 [doi>10.1109/TC.2005.185]
• 13: John W. Lockwood , Naji Naufel , Jon S. Turner , David E. Taylor, Reprogrammable network packet processing on the field programmable port extender (FPX), Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.87-93, February 2001, Monterey, California, United States [doi>10.1145/360276.360304]
• 14: Peter S. Magnusson , Magnus Christensson , Jesper Eskilson , Daniel Forsgren , Gustav Hållberg , Johan Högberg , Fredrik Larsson , Andreas Moestedt , Bengt Werner, Simics: A Full System Simulation Platform, Computer, v.35 n.2, p.50-58, February 2002 [doi>10.1109/2.982916]
• 15: Microsoft Corporation. Scalable Networking: Network Protocol Offload -- Introducing TCP Chimney, Apr. 2004.
• 16: Jeffrey Mogul , Lawrence Brakmo , David E. Lowell , Dinesh Subhraveti , Justin Moore, Unveiling the transport, ACM SIGCOMM Computer Communication Review, v.34 n.1, January 2004 [doi>10.1145/972374.972392]
• 17: M. Otey , S. Parthasarathy , A. Ghoting , G. Li , S. Narravula , D. Panda, Towards NIC-based intrusion detection, Proceedings of the ninth ACM SIGKDD international conference on Knowledge discovery and data mining, August 24-27, 2003, Washington, D.C. [doi>10.1145/956750.956847]
• 18: I. Pratt and K. Fraser. Arsenic: A user-accessible Gigabit Ethernet interface. In Proceedings of IEEE INFO-COM, Apr. 2001.
• 19: Mendel Rosenblum , Stephen A. Herrod , Emmett Witchel , Anoop Gupta, Complete Computer System Simulation: The SimOS Approach, IEEE Parallel & Distributed Technology: Systems & Technology, v.3 n.4, p.34-43, December 1995 [doi>10.1109/88.473612]
• 20: A. G. Saidi, N. L. Binkert, L. R. Hsu, and S. K. Reinhardt. Performance validation of network-intensive workloads on a full-system simulator. In Proceedings of the Workshop on Interaction between Operating System and Computer Architecture, Oct. 2005.
• 21: J. Shafer and S. Rixner. A reconfigurable and programmable gigabit ethernet network interface card. Technical Report TREE0611, Rice University, Dec. 2006.
• 22: Piyush Shivam , Pete Wyckoff , Dhabaleswar Panda, EMP: zero-copy OS-bypass NIC-driven gigabit ethernet message passing, Proceedings of the 2001 ACM/IEEE conference on Supercomputing (CDROM), p.57-57, November 10-16, 2001, Denver, Colorado [doi>10.1145/582034.582091]
• 23: Piyush Shivam , Pete Wyckoff , Dhabaleswar K. Panda, Can User-Level Protocols Take Advantage of Multi-CPU NICs?, Proceedings of the 16th International Parallel and Distributed Processing Symposium, p.88, April 15-19, 2002
• 24: G. Watson, N. McKeown, and M. Casado. NetFPGA: A tool for network research and education. In Proceedings of the Workshop on Architecture Research using FPGA Platforms, Feb. 2006.
• 25: Jeffrey Shafer , David Carr , Aravind Menon , Scott Rixner , Alan L. Cox , Willy Zwaenepoel , Paul Willmann, Concurrent Direct Network Access for Virtual Machine Monitors, Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, p.306-317, February 10-14, 2007 [doi>10.1109/HPCA.2007.346208]
• 26: Ken Yocum , Jeffrey S. Chase, Payload Caching: High-Speed Data Forwarding for Network Intermediaries, Proceedings of the General Track: 2002 USENIX Annual Technical Conference, p.305-317, June 25-30, 2001

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Interfaces

General Terms:
Design, Experimentation

Keywords:
FPGA prototyping, ethernet, network interface cards