Context switch overheads for Linux on ARM platforms

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Context switch overheads for Linux on ARM platforms

Full text

Pdf (201 KB)

Source

Workshop On Experimental Computer Science archive
Proceedings of the 2007 workshop on Experimental computer science table of contents

San Diego, California

Article No. 3

Year of Publication: 2007

ISBN:978-1-59593-751-3

Authors

Francis M. David	University of Illinois at Urbana-Champaign, Urbana, IL
Jeffrey C. Carlyle	University of Illinois at Urbana-Champaign, Urbana, IL
Roy H. Campbell	University of Illinois at Urbana-Champaign, Urbana, IL

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 75, Downloads (12 Months): 184, Citation Count: 1

Additional Information:

abstract references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/1281700.1281703 What is a DOI?

ABSTRACT

Context switching imposes a performance penalty on threads in a multitasking environment. The source of this penalty is both direct overhead due to running the context switch code and indirect overhead due to perturbation of caches. We calculate indirect overhead by measuring the running time of tasks that use context switching and subtracting the direct overhead. We also measure the indirect overhead impact on the running time of tasks due to processor interrupt servicing. Experiment results are presented for the Linux kernel running on an ARM processor based mobile device platform.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	D. Brash. The ARM Architecture Version 6. ARM White Paper, Jan 2002.
	2	M. Co and K. Skadron. The Effects of Context Switching on Branch Predictor Performance. In 2001 IEEE International Symposium on Performance Analysis of Systems and Software, pages 77--84, Nov 2001.
	3	L4 Performance, http://ertos.nicta.com.au/research/14/performance.pm1.
	4	Larry McVoy , Carl Staelin, lmbench: portable tools for performance analysis, Proceedings of the 1996 annual conference on USENIX Annual Technical Conference, p.23-23, January 22-26, 1996, San Diego, CA
	5	Jeffrey C. Mogul , Anita Borg, The effect of context switches on cache performance, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.75-84, April 08-11, 1991, Santa Clara, California, United States
	6	J. K. Ousterhout. Why Aren't Operating Systems Getting Faster As Fast as Hardware? In USENIX Summer, pages 247--256, 1990.
	7	Johan Stärner , Lars Asplund, Measuring the cache interference cost in preemptive real-time systems, Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, June 11-13, 2004, Washington, DC, USA
	8	Texas Instruments OMAP Platform, http://focus.ti.com/omap/docs/omaphomepage.tsp.
	9	A. Wiggins, H. Tuch, V. Uhlig, and G. Heiser. Implementation of Fast Address-Space Switching and TLB Sharing on the Strong ARM Processor. In 8th Asia-Pacific Computer Systems Architecture Conference, Sep 2003.