Accelerating system-on-chip power analysis using hybrid power estimation

ABSTRACT

Fast and accurate power analysis is a critical requirement for designing power-efficient System-on-Chips (SoCs). Current system-level power analysis tools are incapable of generating power estimates under real-life workloads within an acceptable amount of time, even for moderately complex SoCs. Our work addresses this problem by borrowing on emulation, which is a widely used technique to accelerate functional verification. Unfortunately, hardware emulation of all the necessary functions for full SoC power analysis is likely to be infeasible for most systems, due to constraints on emulation capacity, and the lack of emulation-ready, synthesizable models for some SoC components early in the design process.

This paper describes hybrid power estimation, an approach to accelerating SoC power analysis by emulating the functional and power models of a subset of SoC components on an FPGA platform (even a low-cost, off-the-shelf FGPA board). We describe the hardware and software components of the framework, and propose techniques to overcome the challenges posed by limited host-board communication bandwidth. We have implemented a hybrid power estimation framework using a Xilinx Virtex-II Pro emulation platform and software extensions to an HDL simulator, to conduct power analysis of a video decoder SoC. The results indicate 65--332X gains in analysis efficiency over simulation-based power estimation, with no loss in accuracy. Further, we show that the increase in FPGA resource requirements for hybrid power estimation over pure functional emulation are modest.

REFERENCES

• 1: Joel Coburn , Srivaths Ravi , Anand Raghunathan, Power emulation: a new paradigm for power estimation, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065764]
• 2: Vivek Tiwari , Sharad Malik , Andrew Wolfe, Power analysis of embedded software: a first step towards software power minimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.437-445, Dec. 1994 [doi>10.1109/92.335012]
• 3: Milind B. Kamble , Kanad Ghose, Analytical energy dissipation models for low-power caches, Proceedings of the 1997 international symposium on Low power electronics and design, p.143-148, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263310]
• 4: Paul P. Sotiriadis , Anantha P. Chandrakasan, A bus energy model for deep submicron technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.341-350, June 2002 [doi>10.1109/TVLSI.2002.1043337]
• 5: Enrico Macii , Massoud Pedram , Fabio Somenzi, High-level power modeling, estimation, and optimization, Proceedings of the 34th annual conference on Design automation, p.504-511, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266268]
• 6: Marcello Lajolo , Anand Raghunathan , Sujit Dey , Luciano Lavagno, Cosimulation-based power estimation for system-on-chip design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.253-266, June 2002 [doi>10.1109/TVLSI.2002.1043328]
• 7: Yanbing Li , Jörg Henkel, A framework for estimation and minimizing energy dissipation of embedded HW/SW systems, Proceedings of the 35th annual conference on Design automation, p.188-193, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277097]
• 8: Yuichi Nakamura , Kouhei Hosokawa , Ichiro Kuroda , Ko Yoshikawa , Takeshi Yoshimura, A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996655]
• 9: Swapnajit Mittra, Principles of VERILOG PLI, Kluwer Academic Publishers, Norwell, MA, 1999
• 10: "Modelsim 5.7e." http://www.model.com.
• 11: DINI Group, "DN6000K10 Virtex II Pro Based ASIC Prototyping Engine." http://www.dinigroup.com/DN6000k10.php.
• 12: ARM Ltd., "ARM946E-S: Embedded Core with Flexible Cached Memory System and DSP Instruction Set Extensions." http://www.arm.com/products/CPUS/ARM946ES.html.
• 13: Synopsys Inc., "Designware Intellectual Property." http://www.synopsys.com/products/designware/.
• 14: Nikhil Bansal , Kanishka Lahiri , Anand Raghunathan, Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis, Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems, p.513-520, January 06-10, 2007 [doi>10.1109/VLSID.2007.46]
• 15: Nikhil Bansal , Kanishka Lahiri , Anand Raghunathan , Srimat T. Chakradhar, Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models, Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, p.579-585, January 03-07, 2005 [doi>10.1109/ICVD.2005.138]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.4 VLSI Systems

General Terms:
Design, Experimentation, Performance

Keywords:
emulation, power analysis, power estimation, simulation, system-on-chip