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Thousand core chips: a technology perspective
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 44th annual Design Automation Conference table of contents
San Diego, California
SESSION: Thousand-core chips table of contents
Pages: 746 - 749  
Year of Publication: 2007
ISBN ~ ISSN:0738-100X , 978-1-59593-627-1
Author
Shekhar Borkar  Intel Corp, Hillsboro, OR
Sponsors
: The EDA Consortium
: IEEE/CASS/CANDE/CEDA
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 66,   Downloads (12 Months): 322,   Citation Count: 17
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ABSTRACT

This paper presents the many-core architecture, with hundreds to thousands of small cores, to deliver unprecedented compute performance in an affordable power envelope. We discuss fine grain power management, memory bandwidth, on die networks, and system resiliency for the many-core system.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Tschanz J., et al, "Dynamic sleep transistor and body bias for active leakage power control of microprocessors", IEEE Journal of Solid State Circuits, November 2003.
 
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Pham D. et al, "The design and implementation of a first-generation CELL processor", ISSCC 2005.
 
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Vangal et al, "An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS", ISSCC 2007.
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CITED BY  18