Off-chip decoupling capacitor allocation for chip package co-design

ABSTRACT

Off-chip decoupling capacitor (decap) allocation is a demanding task during package and chip codesign. Existing approaches can not handle large numbers of I/O counts and large numbers of legal decap positions. In this paper, we propose a fast decoupling capacitor allocation method. By applying a spectral clustering, a small amount of principal I/Os can be found. Accordingly, the large power supply network is partitioned into several blocks each with only one principal I/O. This enables a localized macromodeling for each block by a triangular-structured reduction. In addition, to systemically consider a large legal position map in a manageable fashion, the map of legal positions is decomposed into multiple rings, which are further parameterized in each block. The decaps are then allocated according to the sensitivity obtained from the parameterized macro-model for each block. Compared to the PRIMA-based macromodeling, experiments show that our method (TBS2) is 25X faster and has 3.04X smaller error. Moreover, our decap allocation reduces the optimization time by 97X, and reduces decap cost by up to 16% to meet the same power-integrty target.

REFERENCES

• 1: H. Zheng and et. al., "On-package decoupling optimization with package macromodels," in Proc. CICC, 2003.
• 2: Jun Chen , Lei He, Noise driven in-package decoupling capacitor optimization for power integrity, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA [doi>10.1145/1123008.1123027]
• 3: Sanjay Pant , Eli Chiprout, Power grid physics and implications for CAD, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1146964]
• 4: Hao Yu , Yiyu Shi , Lei He , David Smart, A fast block structure preserving model order reduction for inverse inductance circuits, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California [doi>10.1145/1233501.1233504]
• 5: P. Feldmann , F. Liu, Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.88-92, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382548]
• 6: Pu Liu , S. X. -D. Tan , Hang Li , Zhenyu Qi , Jun Kong , B. McGaughy , Lei He, An efficient method for terminal reduction of interconnect circuits considering delay variations, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.821-826, November 06-10, 2005, San Jose, CA
• 7: C. Ding, "Spectral clustering, principal component analysis and matrix factorizations for learning," in Int't Conf. on Machine Learning (Tutorial), 2005.
• 8: Hao Yu , Yiyu Shi , Lei He, Fast analysis of structured power grid by triangularization based structure preserving model order reduction, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1146965]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms, Design

Keywords:
PG grid simulation, model order reduction