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Analog placement based on novel symmetry-island formulation
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 44th annual Design Automation Conference table of contents
San Diego, California
SESSION: Modern placement techniques table of contents
Pages: 465 - 470  
Year of Publication: 2007
ISBN ~ ISSN:0738-100X , 978-1-59593-627-1
Authors
Po-Hung Lin  National Taiwan University, Taipei, Taiwan and Springsoft, Inc., Hsinchu, Taiwan
Shyh-Chang Lin  Springsoft, Inc., Hsinchu, Taiwan
Sponsors
: The EDA Consortium
: IEEE/CASS/CANDE/CEDA
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 6,   Downloads (12 Months): 36,   Citation Count: 3
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ABSTRACT

In this paper, we present the first amortized linear-time packing algorithm for the placement with symmetry constraints. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B*-tree representation, we propose automatically symmetric-feasible B*-trees (ASF-B*-trees) to directly model the placement of a symmetry island. Unlike the previous works that can handle only 1D symmetry constraints, our ASF-B*-tree is the first in the literature to additionally consider 2D symmetry. We then present hierarchical B*-trees (HB*-trees) which can simultaneously optimize the placement with both symmetry islands and non-symmetry modules. Unlike the previous works, our approach can guarantee the close proximity of symmetry modules and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B*-tree or an HB*-tree is the same as that for a plain B*-tree (only amortized linear) and much faster than previous works which need at least loglinear time. Experimental results show that our approach achieves the best published quality and runtime efficiency for analog placement.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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F. Balasa and K. Lampaert, "Symmetry within the sequence-pair representation in the context of placement for analog design," IEEE TCAD, vol. 19, no. 3, pp. 721--731, Jul. 2000.
 
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J. M. Cohn, D. J. Garrod, R. A. Rutenbar, and L. R. Charley, "KOAN/ANAGRAM II: New tools for device-level analog placement and routing," IEEE JSSC, vol. 26, pp. 330--342, Mar. 1991.
 
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S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by Simulated Annealing," Science, vol. 220, no. 4598, pp. 671--680, May 1983.
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J.-M. Lin, H.-E. Yi, and Y.-W. Chang, "Module placement with boundary constraints using B*-trees," IEE Proceedings -- Circuits, Devices and Systems, vol. 149, no. 4, pp. 251--256, Aug. 2002.
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S. C. Maruvada, A. Berkman, K. Krishnamoorthy, and F. Balasa, "Deterministic skip lists in analog topological placement," Proc. ASICON, pp. 756--759, Oct. 2005.
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Collaborative Colleagues:
Po-Hung Lin: colleagues
Shyh-Chang Lin: colleagues